Lesson 25/25100%

Course Complete!

You have completed FPGA Fundamentals and Architecture — 25 lessons covering everything from what an FPGA is to building a multi-clock FIR filter with DSP48E1 cascade, BRAM, clock domain crossing, and hardware debug using ILA.

What You Have Learned

Topic Group Lessons Key Concepts Covered
FPGA Basics 1–5 What FPGA is, history, why FPGA, comparisons with MCU, ASIC, and GPU
Xilinx Families and Die 6–7 Spartan, Artix, Kintex, Virtex, Zynq, Versal families; die, package, IO banks, SSI
Logic Fabric 8–13 CLB, Slice L/M, LUT6 INIT, FDRE, CARRY4, F7MUX/F8MUX hierarchy
Routing and Clocks 14–15 Switch matrix, wire segments, BUFG/BUFH/BUFR/BUFIO, MMCM, PLL, CDC
Memory Resources 16–17 RAMB36E1 SDP/TDP/ECC modes vs Distributed RAM (LUT-based) vs SRL32
Hard Blocks 18–20 DSP48E1 pre-adder/multiplier/cascade; HP/HR IO banks; GTX/GTH/CDR/QPLL
Configuration 21–22 Bitstream format, SRAM cells, SPI/BPI/JTAG boot, MultiBoot, partial reconfig
Design and Debug 23–25 Full RTL-to-bitstream flow, timing closure, ILA/VIO debug, architecture walkthrough

Architecture Quick Reference Cheat Sheet

Parameter 7-Series Value UltraScale / UltraScale+ Notes
LUT inputs 6 (LUT6) 6 (LUT6) 64-bit SRAM, dual O5+O6 output
FFs per Slice 8 (FDRE/FDSE/FDPE/FDCE) 8 D-type with CE and synchronous/async SR
Slices per CLB 2 (Slice L + Slice M) 2 Slice M supports LUT RAM and SRL
Carry primitive CARRY4 (4 stages) CARRY8 (8 stages) ~0.1 ns per stage, 5x faster than routing
BRAM type RAMB36E1 (36 Kbits) RAMB36E2 (36 Kbits) Dual-port, ECC, FIFO mode
DSP type DSP48E1 (25x18-bit mult) DSP48E2 (27x18-bit mult) 48-bit accumulator, PCIN/PCOUT cascade
Global clock buffers 32 BUFG per device 24 per SLR H-tree, less than 100 ps skew
Max transceiver rate GTX 12.5 Gbps / GTH 16.375 Gbps GTY 32.75 Gbps QPLL shared per quad (4 channels)
IO bank types HP (max 1.8V) / HR (max 3.3V) HP / HR HP supports DCI on-chip termination
Config interface SPI / BPI / JTAG / SelectMAP Same SPI flash most common in production
Clock skew (BUFG) Less than 100 ps Less than 100 ps H-tree symmetric layout
SPI boot time (A35T) ~2.7 s at 50 MHz Varies by bitstream size Enable compression to reduce by up to 50%

Top 10 FPGA Interview Questions

Q1: What is the fundamental difference between an FPGA and a microcontroller?
An MCU executes instructions sequentially on a fixed processor pipeline — one operation per clock cycle per core. An FPGA implements the hardware datapath in configurable silicon fabric — operations run truly in parallel, with no instruction fetch overhead. An FPGA running at 100 MHz can perform millions of simultaneous operations per clock cycle because every function has its own dedicated hardware path.
Q2: What is a LUT6 and how can it implement any Boolean function of up to 6 inputs?
A LUT6 is a 64-bit SRAM. Its six address inputs A1–A6 select one of the 64 memory cells, and the stored bit appears at the output. The 64 bits encode the complete truth table of any 6-input Boolean function. During bitstream loading, the synthesis tool programs each LUT's 64-bit INIT parameter with the appropriate truth table — this is why FPGAs can implement any logic function without changing hardware.
Q3: How many CARRY4 primitives does a 32-bit ripple-carry adder require in Xilinx 7-series?
8 CARRY4 primitives (each implements 4 full-adder stages: 32 / 4 = 8). They cascade vertically in the same CLB column via CO[3] to CI connections. Total delay is approximately 8 x 0.1 ns = 0.8 ns, versus approximately 4 ns through general routing — making CARRY4 roughly 5x faster for arithmetic operations.
Q4: What is clock domain crossing (CDC) and why is it dangerous?
CDC occurs when a signal generated in one clock domain is sampled by a flip-flop in a different, asynchronous clock domain. The receiving flip-flop may violate its setup or hold time — entering metastability, an undefined state that can randomly resolve to 0 or 1 with no guaranteed timing. The standard fix for single-bit signals is a 2-FF synchronizer. For data buses, use an asynchronous FIFO. Always validate CDC paths with Vivado's report_cdc command.
Q5: What is the difference between Block RAM and Distributed RAM?
Block RAM (RAMB36E1) is dedicated silicon — 36 Kbits per block, synchronous read, dual-port, ECC support, physically in fixed BRAM columns. Distributed RAM uses the LUT SRAM cells in Slice M — 64 bits per LUT, asynchronous read by default, scattered throughout the fabric. Use BRAM for memories larger than a few kilobits; use Distributed RAM for small, low-latency lookups and register files where async read is advantageous.
Q6: What does the pre-adder in DSP48E1 do and why is it important for FIR filters?
The pre-adder computes D ± A before the 25x18-bit multiplier. For a symmetric FIR filter where coefficients satisfy h[k] = h[N-1-k], the pre-adder computes (sample[n-k] + sample[n-(N-1-k)]) before multiplying by h[k]. This halves the number of DSP48E1 primitives needed — a 16-tap symmetric filter needs only 8 DSPs instead of 16.
Q7: Why must FPGA clocks use BUFG instead of general routing fabric?
General routing has 3–5 ns clock skew across a large FPGA — far too much for reliable synchronous design. BUFG drives a dedicated H-tree network with symmetric layout, achieving less than 100 ps skew across the entire device. BUFG also drives dedicated clock inputs on every FF, BRAM, and DSP, bypassing the general routing entirely. Never route clocks through LUT logic or general fabric.
Q8: What is the difference between HP and HR IO banks in Xilinx 7-series?
HP (High Performance) banks: maximum VCCO 1.8V, support DCI on-chip termination, best for DDR, LVDS, and high-speed interfaces. HR (High Range) banks: maximum VCCO 3.3V, no DCI, best for legacy 3.3V interfaces and general GPIO. Never connect a 3.3V signal to an HP bank — it exceeds the 1.8V maximum and can permanently damage the device.
Q9: What is CDR in a GTX transceiver and why is it needed?
CDR (Clock and Data Recovery) is a PLL inside the receiver that extracts the transmitter's clock from the incoming data stream by locking onto data transitions. It is needed because high-speed serial interfaces (PCIe, Ethernet, Aurora) embed the clock in the data — there is no separate clock wire at multi-Gbps speeds. The CDR recovers the transmitter's bit clock with sub-picosecond jitter, allowing the deserializer to correctly sample each bit.
Q10: What does Worst Negative Slack (WNS) mean and what must it be for a design to work reliably?
WNS is the minimum setup margin across all timing paths in the design — the difference between the available time (clock period minus skew) and the actual propagation delay (logic + routing). WNS must be 0.0 ns or positive for timing to be met. Negative WNS means at least one flip-flop is being asked to sample data before it has settled — causing random, non-deterministic failures that are almost impossible to debug in the field.

Final Quiz — 10 Questions

Test your knowledge across all 25 lessons. Score: 0 / 10

1. How many bits are in the SRAM array of a single LUT6?
  • 32 bits
  • 64 bits
  • 128 bits
  • 256 bits
LUT6 has 6 address inputs, so 2^6 = 64 SRAM cells each storing 1 bit. The 64-bit INIT parameter encodes the complete truth table of the implemented function.
2. Which Xilinx 7-series primitive implements four full-adder stages using dedicated carry silicon?
  • F7MUX
  • DSP48E1
  • CARRY4
  • MUXF8
CARRY4 implements 4 full-adder stages using dedicated carry propagation paths at approximately 0.1 ns per stage — 5x faster than the same arithmetic implemented with LUT routing.
3. BUFG provides what maximum clock skew across the entire 7-series device?
  • Less than 1 ps
  • Less than 100 ps
  • Less than 1 ns
  • Less than 5 ns
The BUFG drives a dedicated H-tree network with symmetric layout achieving less than 100 ps clock skew across the entire device. General routing would have 3–5 ns skew — unusable for synchronous design.
4. What is the output accumulator width of DSP48E1?
  • 32 bits
  • 43 bits
  • 48 bits
  • 64 bits
DSP48E1 has a 48-bit accumulator output (P port). The 25x18-bit multiplier produces a 43-bit result, which feeds the 48-bit post-adder/accumulator. The extra bits prevent overflow during accumulation of many products.
5. Which IO bank type in Xilinx 7-series supports DCI (Digitally Controlled Impedance)?
  • HP (High Performance) banks only
  • HR (High Range) banks only
  • Both HP and HR banks
  • Neither — DCI requires external resistors
Only HP banks support DCI in Xilinx 7-series. DCI provides automatic on-chip impedance calibration for interfaces like DDR3/DDR4, eliminating the need for external termination resistors. HP banks are limited to 1.8V VCCO maximum.
6. Which GTX PLL is shared by all four channels in a transceiver quad?
  • CPLL
  • QPLL
  • MMCM
  • PLL
QPLL (Quad PLL) is shared across all 4 channels in a transceiver quad. It is used for line rates above 6.6 Gbps. CPLL is per-channel and used for lower line rates. Both require a dedicated REFCLK pin — not a BUFG-driven clock.
7. Which FPGA configuration mode uses M[2:0] = 000?
  • JTAG
  • Slave SelectMAP
  • Master SPI
  • Master BPI
M[2:0] = 000 selects Master SPI mode — the most common production configuration. The FPGA drives the SPI flash clock and reads the bitstream automatically on power-up. This mode is used in the vast majority of production FPGA boards.
8. MMCM stands for what?
  • Multi-Mode Clock Multiplexer
  • Mixed-Mode Clock Manager
  • Multi-MHz Clock Module
  • Master Mode Clock Multiplier
MMCM stands for Mixed-Mode Clock Manager. It is a phase-locked loop with fractional frequency synthesis, phase adjustment (0–360 degrees in fine steps), spread spectrum support, and up to 7 output clocks. More capable than the simpler PLL primitive.
9. What must Worst Negative Slack (WNS) be for a design to meet timing?
  • As negative as possible (more negative = more margin)
  • Exactly zero
  • Zero or positive (0.0 ns or better)
  • Greater than 1.0 ns for safety margin
WNS must be 0.0 ns or greater (positive). A value of exactly 0.0 ns means the worst path just barely meets timing. Positive WNS means margin remains. Negative WNS means at least one path fails — the design will have random, intermittent hardware failures.
10. In a symmetric 16-tap FIR filter using the DSP48E1 pre-adder, how many DSP48E1 primitives are needed?
  • 4
  • 8
  • 16
  • 32
8 DSPs. A 16-tap symmetric filter has 8 unique coefficient pairs (h[0]=h[15], h[1]=h[14] ...). The pre-adder computes the sample pair sum before multiplying, so each DSP handles one symmetric pair — 16 taps / 2 = 8 DSP48E1 primitives cascaded via PCOUT/PCIN.
0 / 10
questions answered correctly

Capstone Mini Project

Project: 4-Tap FIR Filter on Artix-7 Apply everything from this course in one end-to-end design on XC7A35TCPG236-1 at 100 MHz.

Specification: 4-tap symmetric low-pass FIR filter, 12-bit signed input, 12-bit signed output.
Coefficients (Q12): h[0]=h[3]=256, h[1]=h[2]=2048

Step 1 — RTL: Write fir4.v using 2 DSP48E1 (use pre-adder for symmetric pair). Connect PCOUT of DSP0 to PCIN of DSP1.
Step 2 — Sample Buffer: Use 1 RAMB36E1 in SDP mode (64x12-bit) as a circular sample history buffer.
Step 3 — Testbench: Apply mixed 1 kHz + 30 kHz sine waves. Verify 30 kHz is attenuated at output.
Step 4 — Constraints: Create XDC: 100 MHz clock, LVCMOS33 on input/output pins.
Step 5 — Implement: Run full flow. Confirm synthesis shows exactly 2 DSP48E1 and 1 RAMB36E1. Check WNS at 100 MHz.
Step 6 — Debug: Mark filter output with (* mark_debug = "true" *). Program hardware. Observe filtered output with ILA — verify high-frequency attenuation in real time.

Recommended Learning Path

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