Distributed RAM

What is Distributed RAM?

Every LUT in a 7-series FPGA contains 64 SRAM bits that normally store the truth-table function. In Slice M (the memory-capable slice type), these same SRAM cells can be repurposed as small, writable RAM arrays. Because the SRAM is already present in the silicon, using it as RAM does not "cost" extra area — it changes how an existing LUT is configured.

• Available only in Slice M — approximately 25% of all slices in 7-series devices
• Write: synchronous — data is latched on the rising clock edge via a dedicated write port
• Read: asynchronous by default — purely combinational, no clock required
• Smallest configuration: 32×1-bit using one LUT. Largest common configuration: 256×8-bit using 16 LUTs across 2 Slice M

Available Primitives

Xilinx provides a range of distributed RAM primitives that can be instantiated directly or inferred automatically by Vivado synthesis. Common primitives for 7-series devices:

How Distributed RAM Works

The internal SRAM cells of a LUT normally store the 64-entry truth table for the programmed logic function. In Slice M, additional write-port circuitry exists alongside each LUT:

• A WE (Write Enable) input gates writes to the SRAM cells
• A WCLK input captures the write address and data on the rising edge
• The address inputs double as the LUT inputs for reads — purely combinational, just like a normal LUT lookup
• Multiple LUTs are combined in parallel to achieve wider data widths (e.g., 8 LUTs for 8-bit-wide data)

BRAM vs Distributed RAM: Decision Guide

Choosing between Block RAM and Distributed RAM depends on size, latency requirements, and physical placement needs:

SRL — Shift Register LUT (the hidden gem)

The most underutilized capability of Slice M LUTs is the SRL (Shift Register LUT). A single LUT implements a 32-bit synchronous shift register with a dynamically selectable output tap — something that would otherwise consume 32 flip-flops.

• SRL32: 32-bit shift register in 1 LUT with synchronous shift-in on every clock
• A 5-bit address input selects which stage's output to observe — delay from 1 to 32 cycles
• Vivado infers SRL automatically from shift-register RTL patterns
• Example: a 28-tap audio delay line uses just 1 SRL32 versus 28 individual flip-flops

Synthesis Inference and Attributes

Vivado automatically infers distributed RAM from standard Verilog array syntax. The synthesis tool decides between distributed and block RAM based on size heuristics, but you can override this behavior with attributes:

// Standard inference — Vivado chooses BRAM or Distributed RAM based on size
reg [7:0] mem [0:63];
always @(posedge clk) if (we) mem[addr] <= din;
assign dout = mem[addr];  // async read

// Force Distributed RAM regardless of size
(* ram_style = "distributed" *)
reg [7:0] mem [0:63];

// Force Block RAM
(* ram_style = "block" *)
reg [7:0] mem [0:63];

// Force SRL inference for a shift register
(* srl_style = "srl" *)
reg [31:0] shift_reg;
always @(posedge clk) shift_reg <= {shift_reg[30:0], data_in};

After synthesis, inspect Reports → Utilization → RAM Summary to see each inferred RAM with its primitive type, LUT count, and port configuration.

Same Silicon, Different Function

Both a logic LUT and a distributed RAM LUT use exactly the same 64 SRAM bits. The difference is purely configuration — whether those bits store a truth table or writable data:

Knowledge Check

Practical Exercise

module mem_test (
  input  wire       clk,
  input  wire       we,
  input  wire [5:0] addr,
  input  wire [7:0] din,
  output wire [7:0] dout
);
  reg [7:0] mem [0:63];
  always @(posedge clk) if (we) mem[addr] <= din;
  assign dout = mem[addr];   // async read
endmodule