Lesson 8/2532%
MODULE 8 OF 25 20 MIN FPGA FUNDAMENTALS

FPGA Internal Architecture Overview

Build a complete mental map of every major building block inside an FPGA — CLBs, BRAM, DSPs, clock networks, IO, routing, and transceivers — before diving into each in depth.

The Architecture Map

An FPGA is not a single monolithic circuit — it is an array of specialized, interconnected building blocks. Understanding the role of each block and how they connect is essential before you can efficiently use the device or interpret tool output. This lesson gives you the "30,000-foot view" we will systematically zoom into over the next 17 lessons.

Our reference device for this course is the Artix-7 XC7A200T — a widely used, mid-size 7-series FPGA. Its resource counts give us concrete numbers to anchor our understanding:

CLBs
33,650
= 67,300 Slices
LUTs
134,600
LUT6 primitives
Flip-Flops
269,200
D-type FFs
BRAM
365
× 36Kb = 13,140 Kb
DSP48
740
25×18 MAC units
IO Pins
500
max user IO
GTX
16
transceivers
MMCM
10
+ 10 PLLs

Full Architecture Diagram

graph TD subgraph FPGA_FABRIC["FPGA Internal Architecture (7-Series)"] CLB_ARRAY[CLB Array\nSlices + LUTs + FFs + Carry] BRAM_COL[BRAM Columns\n36Kb Dual-Port RAM] DSP_COL[DSP48 Columns\n25×18 MAC] CLOCK_NET[Clock Network\nMMCM + BUFG + BUFH + BUFR] IO_BANKS[IO Banks\nHP/HR, IOB buffers] GTX_XCVR[GTX Transceivers\nHigh-Speed Serial up to 12.5 Gbps] XADC[XADC\n12-bit Dual-Channel ADC] CFG[Config Logic\nJTAG + SPI + SelectMAP + ICAP] ROUTING[Routing Network\nSwitch Matrix + Interconnect] PCIE[PCIe Hard Block\nGen2 x4/x8 optional] end CLB_ARRAY <--> ROUTING BRAM_COL <--> ROUTING DSP_COL <--> ROUTING CLOCK_NET --> CLB_ARRAY CLOCK_NET --> BRAM_COL CLOCK_NET --> DSP_COL IO_BANKS <--> ROUTING GTX_XCVR --> IO_BANKS CFG --> CLB_ARRAY PCIE <--> ROUTING XADC <--> ROUTING

Building Blocks — Detailed Overview

1. CLB — Configurable Logic Block

The fundamental repeating cell. In 7-series, each CLB contains 2 Slices. Slices come in two flavors: Slice L (logic-only) and Slice M (logic + distributed RAM/SRL). CLBs tile the majority of the die area. The synthesis tool maps your RTL into CLBs; the placer assigns CLBs to physical locations on the die.

2. Slice — The Smallest Independently Routable Unit

Each 7-series Slice contains: 4 LUT6s (6-input look-up tables), 8 storage elements (configurable as D flip-flop or latch), 1 CARRY4 (fast arithmetic carry chain), and wide MUXes (F7MUX, F8MUX) for creating 7- and 8-input functions.

3. LUT6 — 6-Input Look-Up Table

A 64×1-bit memory (2⁶ = 64 entries) that implements any Boolean function of 6 inputs. The configuration bitstream programs the 64 bits. A LUT6 can also be split into two independent LUT5s. In Slice M, LUTs double as 64×1-bit distributed SRAM or 32-bit shift registers.

4. Flip-Flop

Each LUT output feeds a dedicated D flip-flop. Features: configurable clock edge (rising/falling), clock enable (CE), synchronous or asynchronous set/reset (SR). FFs can be bypassed to take the LUT output directly. The 2:1 ratio of FFs to LUTs (8 FFs / 4 LUTs per Slice) allows pipelined designs with ample registers.

5. CARRY4 — Fast Carry Chain

Dedicated carry propagation hardware independent of the routing network. One CARRY4 per Slice, cascading vertically between adjacent Slices. Used for adders, subtracters, counters, comparators. Allows arithmetic to run at near-maximum clock frequency without routing delays limiting performance.

6. BRAM — Block RAM (36Kb)

Dedicated synchronous dual-port RAM primitives. Each 36Kb block can split into two 18Kb blocks. Configurable width/depth: 32K×1, 16K×2, 8K×4, 4K×9, 2K×18, 1K×36. True dual-port operation — both ports can read and write simultaneously to different addresses. Essential for FIFOs, packet buffers, coefficient tables, small lookup memories. BRAM is often the limiting resource in memory-heavy designs.

7. DSP48E1 — Digital Signal Processing Slice (7-Series)

A hardened arithmetic unit containing: 25×18-bit two's complement multiplier, 48-bit accumulator, pre-adder (for symmetric filters), and cascade ports for chaining. One DSP48E1 can implement multiply-accumulate (MAC) in a single clock cycle. FIR filters, complex multipliers, FFTs, and PID controllers map efficiently to DSP48E1 chains.

8. Clock Network — MMCM, BUFG, BUFH

7-series provides 32 global clock networks (BUFG). Each drives a low-skew, high-fanout H-tree across the entire device. MMCM (Mixed-Mode Clock Manager) synthesizes frequencies, adjusts phase, and deskews clocks. BUFH distributes clocks within a single clock region. BUFR supports regional clock division. Correct clock domain design is critical for reliable timing closure.

9. IO Blocks (IOB)

Each user IO pin is backed by a fully configurable IO buffer. Features: programmable drive strength (2mA–24mA), slew rate (SLOW/FAST), pull-up/pull-down, keeper, input delay (IDELAY), differential pair support (LVDS, TMDS), and DDR registers (IDDR/ODDR). HP banks add support for DCI (Digitally Controlled Impedance) for clean DDR termination.

10. GTX Transceivers (7-Series)

High-speed serial transceivers up to 12.5 Gbps per channel. Each GTX has dedicated PMA (Physical Medium Attachment) with SerDes, CDR (Clock Data Recovery), and equalization. Supports standard protocols: PCIe, 10GbE, SATA, Aurora, CPRI, JESD204B. Not available on Spartan-7; available on larger Artix-7 and all Kintex-7/Virtex-7 devices.

11. Routing Network

The programmable interconnect fabric that connects all resources. Consists of wire segments of varying lengths: local (within a CLB column), hex (6-CLB span), double (2-CLB span), and long lines (full device width/height). Switch boxes at wire intersections are configured by the bitstream to create signal paths. Routing consumes a large fraction of the total die area and has the most impact on timing after logic mapping.

7-Series Resource Count Reference

Device LUTs FFs BRAM (Kb) DSP IO GTX Clock Regions
XC7A35T 20,800 41,600 1,800 90 250 — 6
XC7A200T 134,600 269,200 13,140 740 500 16 10
XC7K325T 203,800 407,600 25,700 840 500 16 12
XC7K480T 301,440 602,880 34,380 1,920 520 32 16
XC7V585T 364,800 729,600 50,760 1,260 850 36 18

Resource Distribution Across Families

UltraScale / UltraScale+ Architecture Changes In UltraScale and UltraScale+, Xilinx revised the CLB structure. Each CLB now contains only 1 Slice (down from 2 in 7-series), but each Slice has 8 LUTs (up from 4) and 16 FFs (up from 8). The carry chain becomes CARRY8 (8 bits per slice vs 4). The net result is higher density, better FF-to-LUT ratio, and reduced routing congestion. The hierarchical level "CLB" essentially becomes synonymous with "Slice" in UltraScale terminology.
Engineering Tip: Three-Resource Utilization Check When estimating FPGA size requirements: (1) LUT usage drives CLB count, (2) memory needs drive BRAM count, (3) multiply-heavy code drives DSP count. The device must accommodate ALL THREE — pick the smallest device where all three resources are approximately 50% utilized. This gives headroom for timing closure and future modifications.
Interview Question: CLB vs Slice vs LUT Hierarchy Q: What is the difference between a CLB, a Slice, and a LUT?
A: These are nested architectural levels. CLB (Configurable Logic Block) is the top-level grouping — in 7-series, each CLB contains 2 Slices. A Slice is the smallest independently routable unit — each 7-series Slice contains 4 LUT6s, 8 FFs, and 1 CARRY4. A LUT (Look-Up Table) is the 64-bit memory that implements any 6-input Boolean function. So: 1 CLB = 2 Slices = 8 LUTs = 16 FFs in 7-series.
Common Mistake: Checking Only LUT Utilization Engineers often report "I'm at 60% LUT utilization, there's room." But a design with 60% LUT usage and 95% BRAM usage will fail to fit — BRAM is a hard constraint. Similarly, DSP-heavy designs can exhaust DSPs while LUTs are lightly used. Always check all three resource types in the implementation report, not just LUTs.

Knowledge Check

1. In Xilinx 7-series, how many Slices does one CLB contain?

  • A 1
  • B 2
  • C 4
  • D 8
Correct! In 7-series, each CLB = 2 Slices. In UltraScale/UltraScale+, each CLB = 1 Slice (but each Slice has 8 LUTs instead of 4).

2. What is the capacity of one BRAM in Xilinx 7-series?

  • A 18Kb
  • B 36Kb
  • C 72Kb
  • D 4Kb
Correct! Each BRAM tile is 36Kb and can be used as a single 36Kb block or split into two independent 18Kb blocks. The Artix-7 XC7A200T has 365 × 36Kb = 13,140 Kb total.

3. What is the multiplier size in a DSP48E1 slice (Xilinx 7-series)?

  • A 18×18-bit
  • B 25×18-bit
  • C 32×32-bit
  • D 27×18-bit
Correct! DSP48E1 has a 25×18-bit multiplier (two's complement) with a 48-bit accumulator. DSP58E2 in UltraScale increases this to 27×18-bit.

4. How many global clock buffers (BUFG) does a 7-series FPGA provide?

  • A 8
  • B 16
  • C 32
  • D 64
Correct! 7-series FPGAs provide 32 BUFG (Global Clock Buffer) primitives, allowing up to 32 simultaneously active global clock domains.

5. How many flip-flops are in a single 7-series Slice?

  • A 4
  • B 8
  • C 16
  • D 2
Correct! Each 7-series Slice has 8 flip-flops (2 per LUT output). UltraScale+ Slices have 16 FFs (8 LUTs × 2 FFs each).

6. How many CARRY4 primitives are in one 7-series Slice?

  • A 1
  • B 2
  • C 4
  • D 0 — carry logic is in LUTs
Correct! One CARRY4 per Slice in 7-series. It handles 4-bit carry propagation, cascading vertically between adjacent Slices for wide arithmetic. UltraScale uses CARRY8 (8-bit) per Slice.

Practical Exercise

Resource Estimation: 16-Tap FIR Filter You are designing a 16-tap FIR filter with 16-bit input data and 32-bit fixed-point coefficients, targeting an Artix-7 device.
  • (a) How many DSP48E1 slices are needed? (Each tap requires 1 multiplier + accumulation)
  • (b) How many 18Kb BRAMs are needed to store the 16 coefficients (32-bit each)?
  • (c) At 50% utilization headroom, which XC7A device from the table above would you choose?
Check your estimates by creating a simple FIR filter in Vivado and examining the synthesis resource report.
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