IO Banks

Why IO Banks Exist

Real FPGA systems connect to many different external interfaces — each with its own required voltage level and signaling standard. IO banks solve this by grouping pins into regions, where every pin in a group shares the same supply voltage rail (VCCO). This lets different sides of the FPGA talk to different voltage domains simultaneously.

• Example: DDR4 memory requires 1.2V SSTL; an image sensor uses 1.8V LVDS; a debug connector needs 3.3V LVCMOS
• Three separate IO banks can supply each interface at the correct voltage simultaneously
• Wrong VCCO → signal levels fall outside valid thresholds, causing corruption or IO cell damage

Bank Types: HP vs HR

Xilinx 7-series devices offer two distinct IO bank types, optimized for different use cases:

Common IO Standards

IOB — IO Block Internal Structure

Each physical IO pin is managed by an IO Block (IOB) that contains all the signal conditioning circuitry between the pad and the FPGA fabric:

• IBUF: input buffer with programmable slew rate, drive strength, and optional termination
• OBUF: output buffer with programmable drive strength (2–24 mA) and slew (SLOW/FAST)
• IOBUF: bidirectional — when output-enable (OE=0) the buffer tristates and the pin acts as input
• IOB Flip-Flop: a dedicated FF physically inside the IO cell — captures data before routing delay is added, reducing input setup uncertainty
• IDELAY2 / ODELAY2: programmable delay element with 512 taps × 78 ps per step (7-series), used for source-synchronous timing alignment
• ISERDES / OSERDES: 8:1 serializer/deserializer for source-synchronous interfaces (camera, LVDS video)

Differential Pairs and LVDS

LVDS (Low Voltage Differential Signaling) transmits data as the voltage difference between two adjacent pins (P and N). The differential nature cancels common-mode noise, enabling high speeds at low voltage swings:

• Differential swing: ±350 mV across a 100Ω terminated pair
• P and N pins must be adjacent IO pins in the same bank — the package datasheet identifies valid differential pair locations
• IBUFDS: converts differential LVDS_P / LVDS_N to single-ended for the FPGA fabric
• OBUFDS: drives a differential pair output from a single-ended fabric signal
• Used for: high-speed clocks, MIPI camera data lanes, FMC connectors, DisplayPort auxiliary

XDC IO Constraints

IO pin assignments and electrical standards are specified in the Xilinx Design Constraints (XDC) file using set_property commands. Every user-facing IO port must have a PACKAGE_PIN and IOSTANDARD constraint:

# --- Pin location assignments ---
set_property PACKAGE_PIN T22  [get_ports led[0]]
set_property PACKAGE_PIN U22  [get_ports led[1]]
set_property PACKAGE_PIN V22  [get_ports led[2]]
set_property PACKAGE_PIN W22  [get_ports led[3]]

# --- IO voltage standard ---
set_property IOSTANDARD LVCMOS33 [get_ports {led[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn[*]}]

# --- Drive strength and slew rate (outputs only) ---
set_property DRIVE 8         [get_ports {led[*]}]
set_property SLEW  SLOW      [get_ports {led[*]}]

# --- LVDS clock pair ---
set_property PACKAGE_PIN H4  [get_ports sys_clk_p]
set_property PACKAGE_PIN G4  [get_ports sys_clk_n]
set_property IOSTANDARD LVDS [get_ports sys_clk_p]
set_property IOSTANDARD LVDS [get_ports sys_clk_n]

# --- DDR3 data with DCI termination ---
set_property IOSTANDARD SSTL135_T_DCI [get_ports {ddr3_dq[*]}]

DCI — Digitally Controlled Impedance (HP Banks Only)

DCI is an automatic on-chip termination system available exclusively in HP banks. It calibrates the IO driver and termination impedance to match the PCB trace impedance, eliminating the need for external termination resistors on DDR data buses:

• Calibration is performed via a dedicated VREF pin and an internal reference resistor (RSVP)
• The calibration loop runs continuously during operation and tracks temperature/voltage changes
• Required for DDR3/DDR4 DRAM interfaces — saves dozens of discrete termination resistors on the PCB
• Use with IOSTANDARD SSTL135_T_DCI (DDR3) or SSTL12_T_DCI (DDR4)

IO Timing and IOB Flip-Flop

The IOB flip-flop is a register that lives physically inside the IO block — before the signal enters the general routing fabric. Placing the capture FF in the IOB eliminates the routing delay from pad to fabric from the timing analysis path:

• Vivado automatically places a FF in the IOB when it is the first register after an IBUF in the netlist
• Reduces PCB-to-fabric setup uncertainty, enabling faster interface timing closure
• Check IOB FF usage: Vivado → Report IO, or inspect the post-implementation schematic in the Device view
• Force IOB placement: set_property IOB TRUE [get_cells {ff_inst}]

Common IO Mistakes

• Wrong VCCO voltage: supplying 3.3V to a bank constrained for 1.8V causes signal corruption and may damage IO cells
• Missing IBUF on clock: Vivado DRC error — "clock cannot be driven through LUT" — always use IBUFG or IBUFDS for clock inputs
• 3.3V signal on HP bank: HP banks are rated for 1.8V maximum — exceeding this risks IO cell failure
• Floating unused IOs: unused pins without pull-up/pull-down constraints float randomly, toggling and consuming dynamic power — constrain all unused IOs
• Mismatched IOSTANDARD and VCCO: Vivado DRC catches this, but always verify the bank VCCO in the IO Planning view before generating the bitstream

Knowledge Check

Practical Exercise