Configuration Memory

FPGA fabric is built from SRAM cells — they are volatile, fast, and infinitely rewritable, but they forget everything when power is removed. This lesson explains the bitstream format, how configuration memory is organized into frames, what external non-volatile memory options exist, and advanced topics like partial reconfiguration and bitstream security.

FPGA Configuration Fundamentals

Modern SRAM-based FPGAs — which includes virtually all high-performance devices from Xilinx/AMD, Intel/Altera, and Lattice — store their configuration in on-chip SRAM cells. These cells are fast, can be written millions of times, and offer excellent radiation performance, but they are fundamentally volatile: the instant power is removed, all configuration is lost.

This means every time the FPGA powers on, it must reload its configuration from an external non-volatile memory source. The configuration file — called a bitstream — is computed by the Vivado toolchain and encodes every aspect of the design onto the FPGA fabric.

The SRAM configuration cells program the following aspects of the FPGA:

• LUT INIT values — the 64-bit truth table stored in every LUT6, defining the Boolean function it computes
• Routing switches — which wire segments connect to which logic cells via programmable interconnect points (PIPs)
• IO standards — voltage levels, drive strength, slew rate, differential termination for every IO pin
• Clock settings — BUFG enables, MMCM/PLL multiplier and divider values, BUFR configurations
• BRAM initial contents — if INIT values are specified in RTL, they are embedded directly in the bitstream
• DSP48E1 mode bits — cascade enables, pipeline register enables, operational modes

Bitstream Format

Vivado generates the bitstream as a .bit file (for JTAG/Vivado programming) or a .bin file (for direct SPI flash writing). The binary format is standardized and contains several distinct fields:

• Dummy words and sync word — 0xAA995566 marks the start of valid configuration data; the FPGA searches for this pattern after reset and ignores everything before it
• Header section — .bit files include design name, part number, build date, and Vivado version as ASCII strings before the binary payload
• Configuration packets — type-1 and type-2 packets carry register write commands and bulk data
• FAR (Frame Address Register) — sets the destination frame address before each data write
• FDRI (Frame Data Register Input) — the packet type that carries the actual frame configuration bits
• CRC packets — cyclic redundancy check values verified after each major section; a mismatch aborts configuration

Bitstream sizes scale with device density. The complete bitstream must be loaded sequentially into the configuration controller on every power cycle:

Bitstream encryption is supported via AES-256. When enabled in Vivado, the bitstream payload is encrypted with a 256-bit key stored in battery-backed BBRAM or one-time-programmable eFUSE cells on the device. Only a device programmed with the matching key can decrypt and load the bitstream, protecting proprietary IP against cloning or reverse-engineering.

Configuration Cell Organization

The bitstream is organized into frames — the smallest independently addressable unit of configuration memory. In Xilinx 7-series devices, the frame structure is:

• Each frame = 101 words × 32 bits = 3,232 bits
• Frames are addressed hierarchically: Block Type → Row → Column → Minor frame number within column
• Block types: CLB frames, BRAM data frames, BRAM address frames, IOB frames, clock/CMT frames
• XC7A35T contains approximately 7,000 total frames; XC7K325T contains approximately 24,000 frames

The frame-based organization is what enables partial reconfiguration. By writing only the frames belonging to a specific region, the FPGA can update that region while all surrounding logic continues to operate undisturbed. The FAR register in the configuration controller tracks which frame is currently being programmed.

External Memory Options

Since FPGA configuration is volatile, every production design requires an external non-volatile memory to store the bitstream. The choice of memory type affects boot time, cost, density, board area, and interface complexity:

SPI Flash is the dominant choice for production hardware — it needs only 4 PCB traces (CS_B, CLK, MOSI, MISO), is available from many vendors including Micron, Winbond, and Spansion, and Quad-SPI mode (x4) can halve load times compared to standard SPI. The FPGA's internal configuration controller natively drives SPI flash with no external logic required.

Configuration Modes

Three dedicated MODE pins (M[2:0]) on the FPGA package determine which configuration interface is used at power-on. These pins are sampled after POR deasserts and must be stable before that event. On the PCB they are typically tied to fixed logic levels via 1k–10k pull-up or pull-down resistors:

Bitstream Security

When FPGA designs contain proprietary algorithms or licensed IP, the bitstream must be protected against unauthorized readback, cloning, or reverse-engineering. Xilinx 7-series and later devices provide a layered security architecture:

• AES-256 Encryption — the bitstream is encrypted in Vivado using a 256-bit key. The AES-256 decryption engine is embedded in the FPGA configuration controller and operates transparently during boot. The SPI flash contains only ciphertext — useless without the device key.
• eFUSE key storage — one-time programmable (OTP) eFUSE cells permanently burn the AES key into the device during factory programming. Once programmed, eFUSE keys cannot be erased or read back via any interface. BBRAM provides an alternative battery-backed volatile key store that can be updated in the field.
• JTAG readback disable — bitstream readback and partial readback via JTAG can be permanently disabled via eFUSE programming, preventing IP extraction even if a deployed device is captured.
• Xilinx Secure Boot — available on UltraScale and Zynq devices, combining AES-256 encryption with RSA-2048 or ECDSA-256 authentication. This ensures both confidentiality (no one can read the design) and authenticity (only genuine Xilinx-toolchain-generated bitstreams load).

Partial Reconfiguration (PR)

One of the most powerful features enabled by the frame-based configuration architecture is Partial Reconfiguration (PR). PR allows a designated region of the FPGA — called a Reconfigurable Partition (RP) — to be reconfigured while the rest of the device continues operating without any interruption or glitching.

A partial bitstream is generated by Vivado and contains only the configuration frames that fall within the RP boundaries. When loaded via ICAP (Internal Configuration Access Port) or an external interface, only those frames are overwritten — the surrounding logic is untouched and continues clocking. The RP boundary pins remain stable during reconfiguration, isolating the rest of the design from any transient state.

Common applications of partial reconfiguration:

• Adaptive computing — swap in different processing kernels (FFT, FIR, AES, compression) based on runtime workload without stopping the system
• Multi-function overlays — a single FPGA chip time-multiplexes multiple independent applications by reconfiguring the RP
• Field design updates — update a specific subsystem in a deployed product (e.g., upgrade the signal processing core) without rebooting the host CPU or disrupting live data links
• Fault recovery in space/defense — if radiation-induced errors corrupt a module, reconfigure it from a stored golden image while the rest of the system continues operating

In Vivado, enable PR via: Tools → Enable Partial Reconfiguration → define Reconfigurable Modules for each partition → synthesize each RM independently → implement with PR DRC rules enabled → generate full and partial bitstreams.

Knowledge Check

Practical Exercise