Lesson 13/2552%
MODULE 13 OF 25 12 MIN FPGA FUNDAMENTALS

Carry Chains

Master the CARRY4 primitive — Xilinx's dedicated fast-arithmetic silicon path that implements ripple-carry adders, subtractors, and counters 5× faster than LUT-only logic.

What are Carry Chains?

Binary addition is the most fundamental arithmetic operation in digital logic. When you add two multi-bit numbers, each bit position must account for a carry from the bit below — that carry must propagate from the least-significant bit (LSB) all the way to the most-significant bit (MSB). This is known as ripple-carry propagation.

If you implement a wide adder using only LUTs and general routing fabric, each carry bit has to travel through a LUT output and then through the routing interconnect to reach the next stage. That journey takes approximately 0.5 ns per bit stage. A 32-bit adder would require roughly 16 ns just for carry propagation — completely unacceptable at 500 MHz (2 ns period).

The solution is dedicated carry chain silicon. Xilinx FPGAs include a hardwired path specifically for carry propagation that bypasses general routing entirely. This dedicated path achieves approximately 0.1 ns per carry stage — roughly 5× faster than routing through general fabric. The primitive that implements this fast path is called CARRY4.

Key Numbers at a Glance General routing carry propagation: ~0.5 ns per bit stage. Dedicated CARRY4 chain: ~0.1 ns per bit stage. Each Slice contains exactly one CARRY4 primitive providing 4 carry stages. Four Slices per CLB column = 16-bit carry chain per CLB column.

CARRY4 Primitive Structure

The CARRY4 primitive has a specific set of inputs and outputs designed exclusively for fast chained arithmetic. Understanding each port is essential for knowing how Vivado synthesizes arithmetic operations and how to debug timing failures in adder paths.

graph LR subgraph INPUTS["Inputs"] CI["CI\nCarry In from below"] CYINIT["CYINIT\nChain Init (VCC/GND)"] DI["DI[3:0]\nGenerate — LUT O5"] S["S[3:0]\nPropagate — LUT O6"] end subgraph CARRY4P["CARRY4 Primitive"] ST0["Stage 0\nCarry Mux"] ST1["Stage 1\nCarry Mux"] ST2["Stage 2\nCarry Mux"] ST3["Stage 3\nCarry Mux"] ST0 --> ST1 --> ST2 --> ST3 end subgraph OUTPUTS["Outputs"] CO["CO[3:0]\nCarry Outputs\nCO[3] → next CI"] O["O[3:0]\nSum Outputs"] end CI --> ST0 CYINIT --> ST0 DI --> ST0 DI --> ST1 DI --> ST2 DI --> ST3 S --> ST0 S --> ST1 S --> ST2 S --> ST3 ST0 --> CO ST1 --> CO ST2 --> CO ST3 --> CO ST0 --> O ST1 --> O ST2 --> O ST3 --> O
Port Direction Width Function
CI Input 1 Carry in from the CARRY4 directly below in the same CLB column
CYINIT Input 1 Initialize the chain: VCC for subtraction (CI=1), GND for addition (CI=0)
DI[3:0] Input 4 Data input from LUT O5 outputs — carry generate signals (A AND B)
S[3:0] Input 4 Sum select from LUT O6 outputs — carry propagate signals (A XOR B)
O[3:0] Output 4 Sum outputs — XOR of S[i] and carry-in to that stage
CO[3:0] Output 4 Carry outputs — CO[3] cascades to next CARRY4's CI via dedicated routing

The carry mux logic at each stage follows two simple rules:

  • S[i] = 0: CO[i] = DI[i] — carry generate/kill mode (carry determined by data, not previous stage)
  • S[i] = 1: CO[i] = CI — carry ripple mode (carry passes through from the stage below)

How Fast Arithmetic Works Inside CARRY4

For a 1-bit full adder stage with inputs A[i] and B[i] and carry-in CI:

  • The LUT6 output (O6) computes S[i] = A[i] XOR B[i] — the "propagate" signal fed into CARRY4 S port
  • The LUT5 output (O5) computes DI[i] = A[i] AND B[i] — the "generate" signal fed into CARRY4 DI port
  • CARRY4 combines them: if S[i]=1, carry ripples through from below; if S[i]=0, carry is generated from DI[i]
  • The final sum bit is O[i] = S[i] XOR carry_in_to_stage_i

Since a 7-series LUT6 can produce both O5 and O6 simultaneously (using its dual-output feature), each Slice implements 4 bits of full addition using its 4 LUTs and 1 CARRY4 — with no wasted resources. With 4 Slices per CLB column, that is 16 bits per CLB. A 128-bit adder stacks 8 CLBs vertically; the tools handle column placement automatically.

Column Placement is Automatic Each CARRY4 spans exactly one Slice vertically. Cascade 8 CARRY4s (8 Slices = 2 CLBs) for a 32-bit adder. Vivado's P&R engine automatically constrains cascaded CARRY4 primitives to the same CLB column — you never need manual placement constraints for standard adders.

Operations Implemented by CARRY4

Any digital operation that can be reduced to fast carry propagation benefits from the CARRY4 chain. The following table lists the most common operations the synthesizer maps to CARRY4:

Operation How CARRY4 is Used Verilog Operator
Adder Direct ripple-carry chain with CYINIT=GND sum = a + b;
Subtractor Two's complement: invert B bits, CYINIT=VCC (carry-in=1) diff = a - b;
Accumulator Adder with registered feedback; carry chain per clock cycle acc <= acc + data;
Comparator Subtraction result — sign bit gives greater/less-than gt = (a > b);
Counter Increment via carry chain — very efficient for wide counters cnt <= cnt + 1;
Incrementer CARRY4 with one input tied to 0, carry-in = 1 out = in + 1;
Shift-and-add multiplier Partial sum accumulation uses carry chain per partial product prod = a * b; (small widths)

Cascading Carry Chains for Wide Adders

Wide adders require multiple CARRY4 primitives chained in series within the same CLB column. The cascade mechanism is straightforward: CO[3] of one CARRY4 connects to CI of the next via a dedicated carry routing wire that never touches general fabric.

graph TD CYINIT["CYINIT = GND (add) or VCC (sub)"] C4A["CARRY4 — Bits 3:0\nCI ← CYINIT\nCO[3] → next CI"] C4B["CARRY4 — Bits 7:4\nCI ← CO[3] above\nCO[3] → next CI"] C4C["CARRY4 — Bits 11:8\nCI ← CO[3] above\nCO[3] → next CI"] C4D["CARRY4 — Bits 15:12\nCI ← CO[3] above\nCO[3] = overflow bit"] CYINIT --> C4A --> C4B --> C4C --> C4D
  • CYINIT = GND: carry-in to bit 0 is 0 — standard addition
  • CYINIT = VCC: carry-in to bit 0 is 1 — used in two's complement subtraction (invert B + carry-in of 1)
  • CO[3] of each CARRY4 connects to CI of the one above — dedicated carry wire, ~0.01 ns crossing delay
  • Vivado P&R places all cascaded CARRY4s in the same column automatically — no Pblock needed

Synthesis Inference — Let Vivado Do the Work

In virtually all practical designs, you do not need to instantiate CARRY4 manually. Vivado's synthesis engine recognizes arithmetic operators and maps them to CARRY4 chains automatically. The following code shows both approaches — inferred (recommended) and manual instantiation (advanced only):

// ─── RECOMMENDED: Inferred CARRY4 ─────────────────────────────────────────── // Vivado automatically infers a chain of CARRY4 + LUT6 for the + operator module fast_adder ( input [15:0] a, input [15:0] b, output [16:0] sum // 17-bit: bit 16 captures carry-out (overflow) ); assign sum = {1'b0, a} + {1'b0, b}; // Vivado infers 4x CARRY4 + 16x LUT6 endmodule // ─── ADVANCED ONLY: Manual CARRY4 Instantiation ───────────────────────────── // Only needed for sub-nanosecond critical path tuning. // Ties design to Xilinx 7-series — not portable to UltraScale+ without rewrite. CARRY4 carry_stage0 ( .CYINIT (1'b0), // GND: carry-in to bit 0 = 0 (addition) .CI (1'b0), // Unused when CYINIT drives the first stage .DI (di_3_0), // Generate signals: A[3:0] AND B[3:0] from LUT O5 .S (s_3_0), // Propagate signals: A[3:0] XOR B[3:0] from LUT O6 .CO (co_3_0), // co_3_0[3] feeds next CARRY4's CI .O (sum_3_0) // Sum bits 3:0 );

After synthesis, open the Vivado Synthesis Report and search for CARRY4 in the resource utilization section. For a 16-bit adder you will see exactly 4 CARRY4 instances. For a 32-bit adder, 8 instances.

Best Practice: Trust the Synthesizer Never instantiate CARRY4 manually unless you are optimizing an extremely tight critical path where even inferred logic doesn't meet timing. Vivado infers it correctly from + and - operators. Manual instantiation also ties your design irreversibly to Xilinx 7-series architecture — moving to UltraScale or Intel requires complete rewriting of those modules.
Avoid CARRY4 Misuse Do not use CARRY4 for non-arithmetic functions like priority encoders or one-hot decoders. While technically possible, it wastes resources, complicates timing analysis, and makes cross-device retargeting impossible. Use LUTs for logic; use CARRY4 for arithmetic.

Performance Comparison: Carry Chain vs LUT-Only Adder

The following table compares timing for CARRY4-based adders versus LUT-only implementations at worst-case process/voltage/temperature corner for Xilinx 7-series:

Adder Width CARRY4 Chain Delay LUT-Only Delay Speed Improvement CARRY4 Count
8-bit ~0.8 ns ~4 ns 5× 2
16-bit ~1.6 ns ~8 ns 5× 4
32-bit ~3.2 ns ~16 ns (LUT tree) 5× 8
64-bit ~6.4 ns ~25 ns ~4× 16
128-bit ~12.8 ns ~45 ns ~3.5× 32
Interview Question Q: How many CARRY4 primitives are needed for a 32-bit ripple-carry adder in Xilinx 7-series?

A: 8 CARRY4 primitives. Each CARRY4 handles 4 bits of carry propagation, so 32 ÷ 4 = 8 CARRY4s. Vivado places all 8 in the same CLB column automatically — they span 8 Slices across 2 CLBs (4 Slices per CLB). The total carry propagation delay is approximately 8 × 0.1 ns = 0.8 ns, plus LUT and flip-flop delays.
Animation Placeholder Suggested GIF: ripple-carry animation showing a carry bit propagating from bit 0 to bit 7 during an 8-bit addition, with each CARRY4 stage lighting up sequentially at approximately 0.1 ns intervals. The animation should visually show how carry travels up the silicon column from LSB to MSB entirely within the dedicated carry routing — never touching general routing fabric.

Knowledge Check

1. How many full-adder stages does one CARRY4 primitive implement?

  • A 1 stage
  • B 2 stages
  • C 4 stages
  • D 8 stages
Correct! Each CARRY4 primitive has 4 carry stages — CO[0] through CO[3] — implementing 4 bits of a ripple-carry adder. The name CARRY4 literally refers to these 4 carry stages. Each stage requires one LUT to supply the propagate (O6) and generate (O5) signals.

2. Which signal propagates carry between adjacent CARRY4 primitives in a cascade?

  • A CO[0] to CYINIT of next CARRY4
  • B CO[3] to CI of next CARRY4
  • C O[3] to DI[0] of next CARRY4
  • D S[3] to CI of next CARRY4
Correct! CO[3] — the carry output from the most-significant (top) stage of one CARRY4 — connects directly to the CI (carry input) of the next CARRY4 above it in the column. This connection uses a dedicated carry wire, not general routing fabric, adding essentially zero additional delay.

3. CARRY4 dedicated carry paths are faster than general routing carry propagation by approximately how much?

  • A 2×
  • B 10×
  • C 5×
  • D 20×
Correct! The dedicated CARRY4 path achieves ~0.1 ns per stage versus ~0.5 ns per stage through general routing — a 5× speed improvement. For a 32-bit adder this means 3.2 ns vs 16 ns total carry propagation delay, making the difference between meeting 300 MHz timing and failing it completely.

4. Which Verilog operator causes Vivado to automatically infer a CARRY4 chain during synthesis?

  • A & (bitwise AND)
  • B + (addition operator)
  • C ^ (XOR operator)
  • D >> (right shift)
Correct! The + and - arithmetic operators trigger CARRY4 inference in Vivado. When Vivado sees a multi-bit + operation, it maps it to a chain of CARRY4 primitives plus supporting LUT6/LUT5 configurations — all automatically, with no user intervention required.

5. In CARRY4, what does setting CYINIT = VCC accomplish?

  • A Resets the carry chain to zero
  • B Disables the carry chain output
  • C Initializes the carry chain with carry-in = logic 1 (used for subtraction)
  • D Routes carry through general fabric instead of dedicated path
Correct! CYINIT = VCC sets the initial carry-in to logic 1. This is the key to two's complement subtraction: to compute A − B, you invert all bits of B (producing ~B) and then add with carry-in = 1. The + 1 completes the two's complement negation of B. CYINIT = GND is used for normal addition with carry-in = 0.

6. How many CARRY4 primitives are required to build a 64-bit adder?

  • A 8
  • B 64
  • C 16
  • D 32
Correct! 64 bits ÷ 4 stages per CARRY4 = 16 CARRY4 primitives. These occupy 16 Slices arranged vertically in the same CLB column (4 CLBs × 4 Slices each). Total carry propagation delay: 16 × 0.1 ns ≈ 1.6 ns — well within budget at 300 MHz (3.3 ns period).

Practical Exercise

Exercise — Synthesize a 16-bit Adder and Inspect CARRY4 Inference Write a Verilog module fast_adder with two 16-bit inputs (a, b) and a 17-bit output (sum) where bit 16 captures the carry-out (overflow indicator). Use a simple assign sum = {1'b0,a} + {1'b0,b}; statement.

Synthesize in Vivado targeting any Artix-7, Kintex-7, or UltraScale device. After synthesis completes: (1) open the Synthesis Report and search for "CARRY4" in the resource utilization table — verify you see exactly 4 instances; (2) open the implemented design schematic and trace the CARRY4 cascade from bottom to top of the column; (3) right-click any CARRY4 and select "Highlight Fanout" to visualize the chain; (4) run report_timing -max_paths 5 -path_type full and identify whether the critical path slack is dominated by carry chain delay or by the surrounding LUT/FF delays.

Summary

  • The CARRY4 primitive provides 4 dedicated carry stages per Slice at ~0.1 ns per stage — 5× faster than general routing (~0.5 ns/stage)
  • Ports: CI (carry in), CYINIT (chain init via VCC/GND), DI[3:0] (generate from LUT O5), S[3:0] (propagate from LUT O6), CO[3:0] (carry out), O[3:0] (sum out)
  • CO[3] cascades to the next CARRY4's CI via a dedicated carry wire — no general routing involved
  • Vivado automatically infers CARRY4 chains from Verilog + and - operators — manual instantiation is rarely necessary
  • Supported operations include: adders, subtractors, accumulators, comparators, counters, incrementers, and shift-and-add multipliers
  • A 32-bit adder uses 8 CARRY4s; a 64-bit adder uses 16 — all placed in the same CLB column by Vivado automatically
  • Check the synthesis report for CARRY4 instance counts to verify correct inference after synthesis