Inside an FPGA Chip

Peel back the BGA package to understand the physical silicon — die anatomy, IO banks, SSI multi-die technology, power domains, and clock regions.

Die and Package

Most Xilinx 7-series and UltraScale FPGAs ship in BGA (Ball Grid Array) packages. The BGA has hundreds to thousands of solder balls on its underside — these carry power, ground, and signal connections to the PCB. Inside the package sits the die: the actual patterned silicon chip, mounted and connected via flip-chip bumps or wire bonds.

The die contains all the programmable logic, routing, IO buffers, BRAM, DSP slices, transceivers, clock management, and configuration logic. Its size varies enormously — from a few mm² for a small Spartan-7 to over 800 mm² for a large Virtex-7.

FPGA Die Floor Plan (Annotated)

Simplified top-view floor plan of a Xilinx 7-series FPGA die (not to scale)

SSI Technology — Multi-Die FPGAs

The largest Xilinx FPGAs cannot fit on a single reticle-limited die (silicon manufacturing limits the maximum die area a single exposure can print). To overcome this, Xilinx developed SSI (Stacked Silicon Interconnect) technology.

SSI tiles multiple smaller FPGA dies — called SLRs (Super Logic Regions) — on a passive silicon interposer. Thousands of micro-bumps connect the SLRs to the interposer, which routes signals between them. From the designer's perspective, the device looks like one large FPGA, but signals crossing SLR boundaries travel via SLL (Super Long Lines) and incur extra routing delay (typically 1–2 extra cycles of latency).

Devices using SSI: Virtex-7 2000T, Kintex UltraScale+ KU15P, Virtex UltraScale+ VU9P (3 SLRs), VU13P (4 SLRs).

IO Banks

Xilinx 7-series divides IO pins into banks — groups of approximately 50 pins that share a common IO supply voltage (VCCO). There are two types of banks:

Bank Type	VCCO Range	Use	Speed Grade	Voltage Standards
HP (High Performance)	1.0V – 1.8V	High-speed interfaces (DDR, LVDS, SerDes support)	Up to 1.6 Gbps LVDS	LVCMOS12/15/18, LVDS, SSTL, HSUL
HR (High Range)	1.2V – 3.3V	General purpose, 3.3V interfaces	Up to 1.25 Gbps LVDS	LVCMOS12/15/18/33, LVTTL, SSTL, PCI

Power Rails

FPGA power delivery is more complex than most digital ICs. Multiple independent rails serve different sections of the die:

VCCINT — Core logic supply. 1.0V for 7-series; 0.85V for UltraScale+. Supplies the CLB fabric, routing, and most logic.
VCCAUX — Auxiliary supply. 1.8V. Powers MMCM/PLL, configuration logic, JTAG, and IO logic stages.
VCCO — IO bank supply. Per-bank, variable 1.0V–3.3V. Must match the IO standard used in that bank.
VCCBRAM — Block RAM supply. 1.0V. Separate from VCCINT to allow BRAM retention during partial power-down.
VCCADC — XADC (on-chip ADC) supply. 1.8V. Isolated supply for analog accuracy.

Power Distribution Tree

graph TD VCC[External Power Supplies] --> VCCINT[VCCINT\n1.0V Core Logic] VCC --> VCCAUX[VCCAUX\n1.8V Auxiliary] VCC --> VCCO_HP[VCCO HP Banks\n1.0V–1.8V] VCC --> VCCO_HR[VCCO HR Banks\n1.2V–3.3V] VCC --> VCCBRAM[VCCBRAM\n1.0V Block RAM] VCC --> VCCADC[VCCADC\n1.8V XADC] VCCINT --> CLB[CLB Array\nSlices + Routing] VCCINT --> DSP[DSP48 Slices] VCCBRAM --> BRAM[Block RAM\n36Kb Tiles] VCCAUX --> MMCM[MMCM / PLL\nClock Management] VCCAUX --> CFG[Config Logic\nJTAG + SPI] VCCO_HP --> HP_IO[HP IO Buffers] VCCO_HR --> HR_IO[HR IO Buffers]

Clock Regions

The FPGA fabric is divided into rectangular clock regions. Each clock region spans the full width of the fabric and contains approximately 50 CLBs in height. Each region has its own local horizontal clock buffer (BUFH) that taps from the global clock spine.

Clock regions in Xilinx 7-series devices:

Device	Clock Regions	BUFG Available	MMCM per Region
Artix-7 XC7A35T	6	32	5 total
Artix-7 XC7A200T	10	32	10 total
Kintex-7 XC7K325T	12	32	10 total
Virtex-7 XC7V585T	18	32	18 total

Never Mix Voltages in the Same IO Bank If Bank 34 is set to 3.3V LVCMOS (by your XDC constraint or board VCCO rail), every IO in that bank must use a 3.3V-compatible standard. Mixing, for example, 3.3V LVCMOS and 1.8V SSTL in the same bank causes either immediate device damage or intermittent signal integrity failures. The PCB VCCO rail for that bank determines the operating voltage.

Engineering Tip: Use HP Banks for High-Speed Signals HP (High Performance) IO banks support lower voltage swings (1.0V–1.8V VCCO) and achieve faster edge rates needed for DDR4, LVDS, and high-speed differential interfaces. Place your fastest, most critical signals in HP banks. HR banks are better for mixed-voltage general-purpose IO including 3.3V legacy interfaces.

Interview Question: What is SSI Technology? Q: What is SSI technology and why does Xilinx use it?
A: SSI (Stacked Silicon Interconnect) tiles multiple independent FPGA dies (SLRs — Super Logic Regions) on a passive silicon interposer, connected by thousands of micro-bumps. Xilinx uses it because single FPGA dies cannot exceed the reticle limit (~800 mm² with standard lithography). SSI allows effectively larger devices. The trade-off is that signals crossing SLR boundaries use SLL (Super Long Lines) which add latency, so designers must be mindful of SLR crossing in their floorplan.

Common PCB Mistake: Under-Decoupled Power Rails Always include adequate decoupling capacitors on every VCCINT and VCCO rail — per Xilinx's PCB Design Guidelines (UG483). Under-decoupled FPGAs exhibit intermittent configuration failures, noise-induced bitflips, and reduced reliability at speed. Place 100nF and 10µF caps as close to each power ball group as physically possible on the PCB.

Knowledge Check

1. What does SSI stand for, and what problem does it solve?

A Single Silicon Integration — reduces manufacturing cost
B Stacked Silicon Interconnect — allows larger devices than single-die reticle limits
C Substrate Signal Interconnect — improves PCB routing
D Serialized Silicon Interface — speeds up IO

Correct! SSI = Stacked Silicon Interconnect. Multiple SLR dies are tiled on a silicon interposer, enabling FPGA devices larger than what a single reticle exposure can produce.

2. Which VCCO voltage range is supported by HP (High Performance) IO banks in Xilinx 7-series?

A 1.2V – 3.3V
B 1.0V – 1.8V
C 1.8V – 3.3V
D 0.85V – 1.8V

Correct! HP banks support VCCO from 1.0V to 1.8V. This lower swing enables high-speed standards like DDR4 (1.2V) and LVDS (1.8V). HR banks extend to 3.3V for legacy interfaces.

3. What is the VCCINT voltage for Xilinx UltraScale+ devices?

A 1.8V
B 1.0V
C 0.85V
D 1.2V

Correct! UltraScale+ devices run at 0.85V VCCINT (vs 1.0V for 7-series). The 16nm FinFET process enables this lower core voltage, significantly reducing dynamic power.

4. How many global clock buffers (BUFG) are available in Xilinx 7-series devices?

A 8
B 16
C 32
D 64

Correct! Xilinx 7-series provides 32 global clock buffers (BUFG) per device. This limits you to at most 32 simultaneously active global clock networks, which is usually more than enough.

5. What is an SLR in the context of Xilinx SSI FPGAs?

A Shared Logic Resource — a pool of shared DSP and BRAM
B Serializer Logic Region — transceiver grouping
C Super Logic Region — one individual die in a multi-die SSI FPGA
D Static Logic Register — a set of configuration bits

Correct! SLR = Super Logic Region. Each SLR is a separate silicon die in an SSI FPGA. Signals crossing SLR boundaries travel over SLL (Super Long Lines) on the interposer and add latency.

Practical Exercise

Power Supply Design Exercise Design the power supply network for an Artix-7 XC7A200T on a custom PCB. Using the Xilinx datasheet DS181 as reference, identify and specify:

VCCINT voltage and typical current (medium utilization estimate)
VCCAUX voltage and rail current
VCCO for Bank 34 (used for DDR3L interface at 1.35V)
VCCO for Bank 14 (used for 3.3V LVCMOS general IO)
VCCBRAM voltage and typical current

Sketch the power sequencing order (which rail powers up first?) and identify which rails can share a single voltage regulator.

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