What Is an ASIC?
An
Application-Specific Integrated Circuit (ASIC)
is custom silicon designed and manufactured for one specific purpose. Unlike an FPGA
(which ships as generic programmable fabric), an ASIC is designed transistor by
transistor, laid out in physical layers, and manufactured in a semiconductor fab
with a custom mask set. Once fabricated, the design is fixed forever — there is no
reconfiguration, no field update, no second chance without a new chip.
The processor in your smartphone is an ASIC. The WiFi chip in your laptop is an
ASIC. The Ethernet controller on your network card is an ASIC. Every fixed-function,
high-volume chip in consumer electronics is an ASIC — designed once, manufactured
billions of times, with per-unit costs measured in cents. The performance and power
efficiency of a well-designed ASIC is unmatched by any other technology.
But ASICs are extraordinarily expensive to create. The Non-Recurring Engineering
(NRE) cost — covering EDA tool licenses, verification, physical design, mask set
fabrication, and test program development — ranges from $1M to $50M+ depending on
the process node. At TSMC 5nm, a full mask set alone costs $15M–$20M. This makes
ASICs economically viable only at very high production volumes where the NRE
amortizes to a few cents per unit.
ASIC NRE Cost
$1M–$50M+
Non-recurring engineering: masks, verification, layout, test
ASIC Unit Cost (volume)
$0.10–$10
At millions of units; dies from wafer + packaging + test
FPGA NRE Cost
~$0
Use existing silicon; only pay for engineering time and tools
FPGA Unit Cost
$5–$500+
Each unit is a full FPGA chip; never scales like ASIC
ASIC Time to Market
18–36 mo
From RTL freeze to first production silicon
FPGA Time to Market
Weeks–Months
RTL to working prototype in days; product in months
The FPGA-to-ASIC Transition Strategy
graph TD CONCEPT["Design Concept\n& RTL Development"] --> PROTO["FPGA
Prototype\n(Weeks — Low Cost)\nValidate algorithm\nProve interfaces"] PROTO -->
VALID["Field Validation\n& Customer Testing\nFix bugs via\nbitstream update"] VALID
--> VOL{"Volume\nDecision"} VOL -- "High Volume\n(100K+ units)\nHigh margin" -->
NRE["ASIC Tape-out\n$1M–$50M NRE\n18–36 months\nTSMC/Samsung fab"] VOL -- "Low–Med
Volume\nor fast-changing spec" --> STAY["Stay on FPGA\nUpdate anytime\nZero respin
cost"] NRE --> BRING["Bring-up\n& Qualification\n6–12 months"] BRING --> PROD["Mass
Production\nLow per-unit cost\nFixed silicon forever"] STAY --> UPDATE["Bitstream
Updates\n→ New Features\n→ Bug Fixes\n→ Protocol Changes"] style PROTO
fill:#0f2d1f,stroke:#34d399,color:#94a3b8 style NRE
fill:#2d0f0f,stroke:#f87171,color:#94a3b8 style STAY
fill:#0f1f2d,stroke:#22d3ee,color:#94a3b8
Cost Crossover: FPGA vs ASIC
Performance and Efficiency: The ASIC Advantage
When it comes to raw performance, power efficiency, and silicon area, an ASIC
designed for a specific function wins decisively. The reason is
programmability overhead: every LUT in an FPGA requires 6–16 SRAM cells to
store its truth table, plus programmable routing multiplexers that add delay. An
ASIC uses the minimum number of transistors needed for the function — no
configuration overhead, no routing indirection.
Quantitatively: equivalent logic in an ASIC consumes 3–10x less power, occupies
10–30x less silicon area, and achieves 3–5x higher clock frequency compared to the
same logic in an FPGA at the same process node. These numbers explain why
billion-unit consumer chips (SoCs, WiFi, DRAM controllers) are always ASICs — at
that scale, the efficiency difference justifies enormous NRE investment.
FPGA vs ASIC — Full Comparison
| Parameter |
FPGA |
ASIC |
| NRE Cost |
~$0 (use existing silicon) |
$1M–$50M+ per design / node |
| Unit Cost |
$5–$500+ (never scales) |
$0.01–$20 at high volume |
| Time to First Silicon |
Days (load bitstream) |
18–36 months from RTL freeze |
| Time to Working Product |
Weeks–months |
24–48 months total |
| Performance (clock) |
100–700 MHz |
1–5 GHz at advanced nodes |
| Power Efficiency |
Baseline (1x) |
3–10x better (less overhead) |
| Silicon Area |
10–30x larger than ASIC equivalent |
Minimum area for function |
| Bug Fix Cost |
$0 — fix RTL, reload bitstream |
$2M–$10M per respin (new masks) |
| Feature Updates |
Any time, zero cost |
Impossible without new tape-out |
| Design Risk |
Low — iterate fast, fail cheap |
Extremely high — one shot per $10M |
| Volume Break-even |
Wins at <50K–500K units |
Wins at >50K–500K units |
| Product Life |
FPGA devices available 15–20 years |
Fixed forever after tape-out |
| Design Flow |
RTL → Synthesis → P&R (vendor tool) |
RTL → Synthesis → Physical design → DRC/LVS → Tape-out |
| Design Team Size |
1–10 engineers |
20–500+ engineers (physical design, DFT, packaging) |
Engineering Tip — The Industry Standard Strategy
The textbook approach for hardware products: (1) Prototype the design on FPGA. (2)
Validate functionality, find and fix bugs with bitstream updates. (3) Field-test
with real customers. (4) Only then — if volume justifies the NRE — commit to an ASIC
tape-out. Never tape out an ASIC without FPGA validation first. No exceptions.
Critical Warning — ASIC Respin Risk
ASIC respins (manufacturing a corrected chip after a bug is found in silicon) cost
$2M–$10M each and add 6–12 months to schedule. A single functional bug, a timing
violation, or an incorrect assumption about power can cause a respin. Many startups
have been destroyed by this. FPGAs eliminate respin risk entirely — fix the RTL and
reload the bitstream the same day.
Interview Question
Q: At what production volume does an ASIC become economically better than an
FPGA?
A: It depends on the ASIC NRE cost and FPGA unit cost. Typical crossover is
50,000–500,000 units. Example: ASIC NRE = $5M, ASIC unit = $2, FPGA unit = $100.
Break-even = $5M / ($100 - $2) = ~51,000 units. Above 51K units, ASIC is cheaper.
Below, FPGA wins. You must also factor in: time-to-market, design risk, feature
update needs, and product lifecycle.
Industry Reality
Many chips marketed as "ASICs" — including Apple's A-series processors — were
extensively validated on FPGA emulation farms before tape-out. Apple, AMD, and Intel
use rack-mounted FPGA arrays (running at 1/10th the target frequency) to run
millions of hours of software and hardware validation before committing a single
dollar to mask sets. FPGA validation is not a startup technique — it's how the best
chip companies in the world work.
Risk Comparison Matrix
Knowledge Check
1. What does NRE stand for in the context of ASIC development?
-
Net Recurring Expense
-
Non-Recurring Engineering cost
-
New Respin Evaluation
-
Nano-Reduced Element cost
Correct! NRE = Non-Recurring Engineering. These are one-time costs incurred once
regardless of production volume: EDA tool licenses, design verification, physical
layout, mask set fabrication ($5M–$20M for leading nodes), and test program
development. NRE is amortized across all units sold.
2. At high production volumes (millions of units), which has a lower per-unit
cost?
-
FPGA — no NRE means lower total cost
-
ASIC — low per-unit cost amortizes the NRE investment
-
They cost the same at high volume
-
FPGA — because ASIC performance advantages reduce units needed
Correct! At high volume, ASIC wins decisively. A consumer chip ASIC can cost
$0.50–$2 per unit at tens of millions of units. An equivalent FPGA costs $20–$200.
Once NRE is amortized, the ASIC's low manufacturing cost per die makes it
economically dominant.
3. Which technology gets a product to market faster?
-
FPGA — weeks to months versus 18–36 months for ASIC
-
ASIC — automated tools reduce development time
-
They are equivalent — both take 6–12 months
-
ASIC — fewer design iterations are needed
Correct! FPGA time-to-market is dramatically faster. An FPGA design can be
prototyped in days and reach production in weeks to months. An ASIC requires 18–36
months minimum from RTL freeze to first production silicon — and that's assuming
no respins. In fast-moving markets, FPGA's time advantage can be worth more than
ASIC's cost advantage.
4. What is the typical development time from RTL freeze to first production ASIC
silicon?
-
1–3 months
-
6–12 months
-
18–36 months
-
5–10 years
Correct! ASIC development from RTL freeze to production silicon takes 18–36
months. This includes: front-end design (6–12 months), physical design and signoff
(6–12 months), mask set ordering and fab (3–5 months), silicon bring-up and
qualification (3–6 months). Complex SoCs can take 4–5 years.
5. An ASIC can be updated to fix a bug after it has been manufactured. True or
False?
-
True — via in-system programming similar to FPGA
-
False — once an ASIC is manufactured, the silicon is fixed forever
-
True — if the ASIC includes embedded Flash for configuration
-
Partially true — metal layer ECOs can patch some bugs
Correct — False! An ASIC's logic is permanently defined by its mask set. A logic
bug requires a full respin (new masks = $2M–$10M). Metal ECOs (Engineering Change
Orders) can patch very minor issues by changing only the top metal layers (~$500K)
but cannot fix fundamental logic errors. Some ASICs include embedded Flash or ROM
for firmware, but the hardware logic itself is fixed.
6. An ASIC NRE is $10M. ASIC unit cost is $3. FPGA unit cost is $200. At what unit
volume does ASIC break even with FPGA?
-
~5,000 units
-
~25,000 units
-
~51,000 units
-
~500,000 units
Correct! Break-even = NRE / (FPGA unit cost − ASIC unit cost) = $10,000,000 /
($200 − $3) = $10,000,000 / $197 ≈ 50,761 units. Above ~51K units, ASIC total cost
is lower. Below, FPGA total cost is lower. This formula is the core of any FPGA vs
ASIC business case.
Practical Exercise — Cost Modeling
Lesson Summary