Lesson 3/2512%
MODULE 3 OF 25 12 MIN FPGA FUNDAMENTALS

FPGA vs Microcontroller (MCU)

Compare the fundamental architectures, execution models, performance characteristics, and cost profiles of FPGAs and microcontrollers to know exactly when to use each.

Learning Objectives

  • Contrast the Von Neumann (MCU) and dataflow (FPGA) execution models at the architectural level
  • Explain why MCU execution is sequential and FPGA execution is parallel
  • Compare FPGA and MCU across: clock speed, parallelism, power, cost, and development time
  • Identify the programming languages and toolchains used for each platform
  • Recognize scenarios where combining MCU and FPGA (Zynq SoC) is the optimal choice
  • Apply a decision framework to select between MCU and FPGA for given design requirements

Two Fundamentally Different Machines

A microcontroller (MCU) and an FPGA are both programmable silicon devices, but they represent completely different philosophies of computation. Understanding the distinction at the architectural level — not just as a checklist — is what separates engineers who make good technology choices from those who reach for the wrong tool.

An MCU implements the Von Neumann architecture: a fixed CPU core, fixed memory (Flash + SRAM), and fixed peripherals (UART, SPI, I2C, ADC). You write firmware in C/C++ that the CPU executes sequentially — one instruction at a time. The hardware never changes; only the software changes. An ARM Cortex-M4 running at 168 MHz executes at most one instruction per clock cycle (with limited 2-wide superscalar on some variants). It's fast, but fundamentally sequential.

An FPGA implements a configurable dataflow architecture: you describe hardware circuits in RTL (VHDL or Verilog), synthesize them into gates and flip-flops, and the FPGA fabric becomes that circuit. There is no instruction pointer. Every LUT, flip-flop, and DSP slice in your design evaluates every clock cycle simultaneously. You're not programming a computer — you're designing a computer.

Architecture Side by Side

Microcontroller (MCU)

  • Fixed CPU core (ARM Cortex-M, RISC-V, AVR)
  • Fixed on-chip Flash memory (16KB–2MB)
  • Fixed on-chip SRAM (4KB–1MB)
  • Fixed peripherals: UART, SPI, I2C, USB, ADC, PWM
  • Fixed clock domains (usually 1–3)
  • Sequential instruction execution
  • Interrupt-driven event handling
  • Power: µW (sleep) to ~500mW (active)
  • Cost: $0.10–$20 per unit
  • Dev language: C/C++/MicroPython

FPGA

  • Configurable LUT array (thousands to millions of LUTs)
  • Programmable Block RAM (BRAM, 36Kb per block)
  • Hardened DSP slices (18x18 or 27x18 multipliers)
  • Flexible I/O supporting 100+ voltage standards
  • Multiple independent clock domains (hundreds)
  • True parallel evaluation every clock cycle
  • Hardware interrupt response (zero latency)
  • Power: 100mW–10W typical
  • Cost: $5–$500+ per unit
  • Dev language: VHDL, Verilog, SystemVerilog, HLS

Internal Architecture Comparison

graph LR subgraph MCU["Microcontroller"] direction TB CPU["CPU Core\n(Fetch → Decode → Execute)"] --> SRAM["SRAM\n(Data)"] CPU --> FLASH["Flash\n(Firmware)"] CPU --> PER["Fixed Peripherals\nUART · SPI · I2C · ADC · PWM"] CPU --> BUS["System Bus\n(Sequential Access)"] end subgraph FPGA_chip["FPGA"] direction TB LUT["LUT Array\n(Combinational Logic)"] --> FF["Flip-Flops\n(Registered State)"] FF --> BRAM["Block RAM\n(Configurable)"] FF --> DSP["DSP Slices\n(Hardened MACs)"] LUT --> IO["Programmable IO\n(Any Standard)"] end style MCU fill:#0f2040,stroke:#22d3ee style FPGA_chip fill:#1a0f40,stroke:#818cf8

Performance: Clock Speed vs Actual Throughput

Clock speed comparisons between MCU and FPGA are misleading without context. An MCU at 480 MHz (STM32H7) is impressive — but it executes one instruction per cycle. An FPGA at 250 MHz might have 10,000 DSP slices all running multiply-accumulate simultaneously. The relevant metric is work done per second, not cycles per second.

For a 16-channel audio mixer running 256-tap FIR filters per channel: an MCU needs to execute 16 × 256 × 48,000 = 196.6 million MACs per second. An STM32H7 at 480 MHz with DSP instructions can sustain roughly 480 MMAC/s — it handles the load, but uses ~40% of CPU time on filtering alone, leaving little headroom. An FPGA implements 16 × 256 = 4,096 parallel MAC units, completing all 16 filter channels simultaneously in a single clock cycle at any frequency above 50 kHz — leaving 99.9% of the FPGA fabric available for other functions.

Head-to-Head: Capability Radar

Comprehensive Comparison Table

Parameter Microcontroller (MCU) FPGA
Architecture Von Neumann — fixed CPU, fixed memory Dataflow — configurable logic fabric
Execution Model Sequential instruction fetch/decode/execute Parallel — all logic evaluates every clock cycle
Clock Speed 8 MHz – 480 MHz (single core) 50 MHz – 700 MHz per clock domain (hundreds of domains)
Parallel Operations 1–8 (with SIMD/DSP instructions) Thousands to millions simultaneously
Programming Language C, C++, Assembly, MicroPython, Rust VHDL, Verilog, SystemVerilog, HLS (C++), Vivado IP
Memory Fixed Flash (16 KB–2 MB) + SRAM (4 KB–1 MB) Configurable BRAM (kilobits–megabits), distributed RAM, external DDR
Power (active) 1 mW – 500 mW 100 mW – 10 W (design-dependent)
Power (sleep) 1 µW – 100 µW ~50 mW static (SRAM cells always powered)
Unit Cost $0.10 – $20 $5 – $500+
Boot/Start Time <1 ms (from cold) 10–100 ms (bitstream load from SPI Flash)
Custom Interfaces Limited to built-in peripherals; bit-bang costly Any voltage standard, any protocol, any timing
Real-Time Timing Yes (bare metal), No (with RTOS jitter) Absolute — hardware guarantees timing
Development Time Hours to days (familiar toolchain) Days to months (RTL + synthesis + P&R + timing closure)
Debugging Easy — JTAG/SWD, printf, GDB Complex — ILA (Integrated Logic Analyzer), simulation required
Best For Control logic, UI, simple protocols, IoT, low power Data processing, custom protocols, high throughput, parallel algorithms
The Best of Both Worlds Many real-world products use MCU + FPGA together: the MCU handles system management, user interface, and control logic (running embedded Linux or RTOS); the FPGA handles data-plane acceleration, custom interfaces, and real-time signal processing. AMD Xilinx Zynq-7000 and Zynq UltraScale+ MPSoC put both on the same die — ARM Cortex-A9/A53 processors tightly coupled to programmable logic fabric.
Common Mistake Don't design a 10 MHz SPI controller or a simple PWM generator in an FPGA when a $0.50 MCU would do the job identically. FPGAs make engineering sense when the requirements include features impossible or impractical on an MCU: massively parallel data paths, sub-100 ns latency, 100+ Gbps throughput, or non-standard electrical interfaces.
Interview Question Q: Can an MCU implement a custom protocol like a proprietary sensor interface?
A: Yes — via bit-banging (software toggling of GPIO pins). But this approach ties up 100% of the CPU during transmission, adds timing jitter from interrupt latency, and cannot exceed a few MHz. An FPGA implements the protocol as dedicated hardware with zero CPU overhead, deterministic timing, and can run at hundreds of MHz. For production systems where the CPU needs to do other work, FPGA wins.
Engineering Tip — The Zynq Solution When your design needs both control logic (boot, management, user interface) and data processing (signal processing, protocol acceleration), the AMD Xilinx Zynq architecture is purpose-built. The Processing System (PS) runs Linux or FreeRTOS on ARM cores; the Programmable Logic (PL) implements your custom hardware. They communicate via AXI4 buses with <1 µs latency. One chip, two paradigms, both optimal.

Selection Guide: MCU or FPGA?

Scenario A
IoT temperature/humidity sensor that transmits via LoRaWAN every 5 minutes. Battery powered, 5-year life target.
Choose MCU (e.g., STM32L0). Ultra-low power sleep mode (1 µA), built-in LoRa radio SPI, simple firmware in C. An FPGA cannot sleep to µA levels due to SRAM static power. There is zero computational challenge here that needs FPGA parallelism.
Scenario B
Real-time 4K@60fps video codec (H.265 encode/decode) for a broadcast camera.
Choose FPGA (e.g., Xilinx UltraScale+). 4K@60fps H.265 encoding requires ~10 billion operations per second. No MCU is close to sufficient. FPGA implements the transform, quantization, entropy coding, and motion estimation engines as parallel hardware pipelines.
Scenario C
Motor controller for a 3-phase BLDC motor with 10 kHz PWM update rate and basic PID loop.
Choose MCU (e.g., STM32G4 with motor control unit). 10 kHz PID updates take 100 µs — well within MCU capability. Built-in advanced timer/PWM hardware, low-cost, mature motor control libraries. FPGA is overkill.
Scenario D
400 Gbps network packet processor for a data center switch.
Choose FPGA (e.g., Xilinx UltraScale+ VU9P). 400 Gbps = processing a 64-byte packet every 1.28 nanoseconds. No MCU, no CPU, no GPU can do this. FPGA implements the packet parser, forwarding table lookup (TCAM), QoS shaper, and statistics counters as dedicated parallel hardware at wire rate.

Knowledge Check

1. How does a microcontroller execute a program compared to an FPGA?
  • MCU executes instructions sequentially; FPGA evaluates all logic in parallel
  • MCU executes in parallel; FPGA executes sequentially
  • Both execute instructions sequentially but at different speeds
  • Both evaluate all logic in parallel simultaneously
Correct! An MCU has a fixed CPU core that fetches and executes instructions one at a time (fetch → decode → execute). An FPGA has no instruction pointer — every LUT and flip-flop evaluates simultaneously every clock cycle. This is the fundamental architectural difference.
2. Which platform provides true parallel hardware execution for thousands of simultaneous operations?
  • Microcontroller with SIMD extensions
  • FPGA with custom parallel logic fabric
  • MCU with dual-core symmetric multiprocessing
  • MCU with DMA controller offload
Correct! FPGAs provide true spatial parallelism — you instantiate as many hardware operators as the design requires, and all of them run simultaneously. SIMD and SMP on MCUs provide limited parallelism (4–16 ways at most), while an FPGA can have millions of parallel logic operations.
3. MCUs generally consume less power than FPGAs. Is this true?
  • True — especially in sleep modes, MCUs reach µW; FPGAs have ~50 mW static power minimum
  • False — FPGAs are always more power efficient due to parallelism
  • True — MCUs always consume less power regardless of the task
  • False — they consume exactly the same power for equivalent tasks
Correct — True! MCUs in sleep mode consume as little as 1 µA. FPGAs cannot reach this because their SRAM configuration cells must remain powered to maintain the design. FPGA static (quiescent) power is typically 50 mW–500 mW minimum. For battery-powered IoT, MCU wins decisively.
4. What hardware description languages are used to program FPGA fabric?
  • C, C++, Python
  • Assembly and machine code
  • VHDL, Verilog, SystemVerilog (and HLS for C++ synthesis)
  • Java and Kotlin (for JVM-based toolchains)
Correct! FPGA design uses Hardware Description Languages (HDLs): VHDL (IEEE standard, verbose, strongly typed), Verilog (IEEE standard, concise, C-like syntax), and SystemVerilog (superset of Verilog with verification features). High-Level Synthesis (HLS) tools like Xilinx Vitis HLS also accept C++ and compile to RTL.
5. For a battery-powered soil moisture sensor that sends data over Bluetooth LE every 30 seconds, which is the better choice?
  • Microcontroller — low power sleep, built-in BLE radio, simple task, µA sleep current
  • FPGA — more flexible, can implement custom BLE stack in hardware
  • FPGA with external BLE module — best of both worlds
  • Either — they perform identically for this use case
Correct! MCU (e.g., Nordic nRF52840) is the clear winner. It includes a BLE radio, ARM Cortex-M4 core, ADC for sensor reading, and can sleep at 2 µA — enabling a 5-year battery life on a coin cell. An FPGA cannot achieve µA sleep power, costs 10x more, and offers no advantage for this simple periodic-sensing task.
6. Which AMD Xilinx device family combines ARM processor cores with FPGA fabric on the same chip?
  • Artix-7
  • Kintex UltraScale
  • Zynq-7000 and Zynq UltraScale+ MPSoC
  • Virtex UltraScale+
Correct! Zynq-7000 contains dual ARM Cortex-A9 + 28nm FPGA fabric. Zynq UltraScale+ MPSoC contains quad ARM Cortex-A53 (APU) + dual Cortex-R5F (RPU) + 16nm FPGA fabric. These are SoC FPGAs — true heterogeneous compute platforms that eliminate the need for separate MCU + FPGA components.

Practical Exercise — Technology Selection

Scenario-Based Selection Exercise

For each scenario below, choose MCU, FPGA, or Zynq SoC. Write a 2–3 sentence justification addressing: computational requirement, power budget, cost sensitivity, and any custom interface needs.

A
400 Gbps Ethernet packet processor for a data center top-of-rack switch. Must classify packets at wire rate, support ACLs and QoS. Latency budget: <100 ns port-to-port.
B
IoT soil moisture sensor deployed in an agricultural field. Reads an analog sensor every 60 seconds, transmits data via LoRaWAN. Must run 3 years on 2 AA batteries.
C
Real-time 4K@60fps H.265 video codec for a professional broadcast camera. Must encode from a CMOS sensor (custom MIPI interface) and output via 12G-SDI.
D
Smart industrial motor controller: runs a 20 kHz FOC (Field-Oriented Control) algorithm for a servo drive AND hosts a web interface for configuration AND runs EtherCAT real-time fieldbus (sub-100 µs cycle time). All three simultaneously.
Hint for Scenario D This is a classic Zynq use case: the ARM processor handles the web UI and Linux networking; the FPGA fabric implements the 20 kHz FOC loop and the EtherCAT slave controller in dedicated hardware — all on one chip.

Lesson Summary

Key Takeaways

  • MCU = Von Neumann machine: fixed CPU + fixed peripherals, sequential instruction execution in C/C++
  • FPGA = configurable dataflow fabric: custom parallel hardware described in RTL, all logic evaluates simultaneously
  • MCU wins for: low power, simple control, standard protocols, IoT, short development cycles, cost sensitivity
  • FPGA wins for: parallel data processing, custom protocols, high throughput, sub-µs latency, custom electrical interfaces
  • FPGA static power (~50 mW+) makes MCU the only viable choice for battery-powered low-duty-cycle applications
  • Zynq SoC (ARM + FPGA on-die) is the optimal solution for designs requiring both control and data-plane functions
  • MCU development takes hours–days; FPGA design takes days–months due to RTL, synthesis, and timing closure complexity
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