DSP Slices

What is a DSP Slice?

A DSP Slice is a dedicated silicon block for high-speed arithmetic — it is not built from LUTs or flip-flops. Implementing the equivalent function in LUT fabric would require 100+ LUTs and would run at a fraction of the speed. DSP slices give you that arithmetic free of LUT cost and at clock frequencies exceeding 700 MHz.

• Xilinx 7-series primitive: DSP48E1
• UltraScale / UltraScale+: DSP48E2 (wider A input: 34 bits vs 30 bits)
• Device counts: Artix-7 — 90 to 740 DSPs; Kintex-7 — 240 to 3600 DSPs; Zynq-7000 — 80 to 2020 DSPs

DSP48E1 Internal Architecture

The DSP48E1 data path has three main computation stages, each of which can be independently pipelined:

1. Pre-adder: computes D ± A, producing a 27-bit result before the multiplier — allows (A+D)×B without an extra LUT adder
2. Multiplier: 25×18-bit signed multiplier producing a 43-bit product
3. Post-adder / accumulator: computes P = X + Y + CARRYIN where X and Y are selected from the muxes below

• X mux inputs: M (multiplier output), P (feedback for accumulate), A:B (48-bit concatenation), 0
• Y mux inputs: C input, P (cascade), 0
• Total output width: 48 bits

Key Input Ports

Pipeline Registers and Timing

DSP48E1 has three optional pipeline register stages. Enabling all three stages dramatically increases the achievable clock frequency at the cost of added latency:

• Stage 1: A1 / B1 registers — after the input ports
• Stage 2: A2 / B2 / M registers — after the pre-adder and multiplier
• Stage 3: P register — at the output of the post-adder

PCIN/PCOUT Cascade — Building Multi-DSP Architectures

Each DSP48E1 has dedicated 48-bit cascade wires that connect directly to the adjacent DSP above and below in the column. Using PCOUT → PCIN avoids the general routing fabric entirely and adds zero routing delay:

• PCOUT[47:0] of DSP_N connects to PCIN[47:0] of DSP_N+1
• Zero additional routing delay — the cascade wire is hardwired between adjacent DSPs
• FIR filter implementation: each tap uses one DSP, PCOUT carries the running sum to the next tap

What DSP48E1 Implements

Synthesis Inference

Vivado automatically infers DSP48E1 primitives from common arithmetic patterns in Verilog or VHDL:

// Simple multiply — infers 1 DSP48E1
assign p = a * b;

// Multiply-accumulate — infers DSP48E1 with P feedback
always @(posedge clk)
  p_reg <= p_reg + a * b;

// Force DSP inference
(* use_dsp = "yes" *)
wire [47:0] result;
assign result = a * b + c;

// Prevent DSP inference (use LUT fabric instead)
(* use_dsp = "no" *)
wire [17:0] product;
assign product = x * y;

After synthesis, check the Vivado Synthesis Report → Primitive Instantiation table for DSP48E1 count. Also search the synthesis log for "DSP48E1" to see which signals were mapped.

FIR Filter Implementation

A direct-form FIR filter computes y[n] = Σ h[k] × x[n−k]. Each tap requires exactly one multiply-accumulate operation — mapping directly to one DSP48E1 per tap with PCOUT cascade for the accumulation:

• Coefficient h[k] is preloaded into the A or B port (or stored in a small distributed RAM)
• Delayed input sample x[n−k] is passed from a shift register chain
• PCOUT carries the running partial sum from tap to tap with zero routing overhead
• Total DSPs for an N-tap FIR = N

AI / ML Acceleration

Modern FPGA AI inference engines exploit DSP48E1 in two key ways:

• INT8 packing: two signed 9-bit values can be packed into the 18-bit B input, enabling two multiply-accumulate operations per DSP per cycle
• MACC chains: cascaded PCOUT chains implement dot products for fully-connected and convolution layers
• Kintex UltraScale+ KU15P: 5,520 DSPs → approximately 170 GOPS at INT8 precision

Knowledge Check

Practical Exercise

module fir16 #(parameter TAPS=16) (
  input  wire        clk, rst,
  input  wire [15:0] x_in,
  output reg  [47:0] y_out
);
  reg  [15:0] h [0:TAPS-1];  // coefficients
  reg  [15:0] xd[0:TAPS-1];  // delay line
  integer i;

  // Load coefficients (LPF values)
  initial begin
    h[0]=16'd100; h[1]=16'd200; // ... etc
  end

  always @(posedge clk) begin
    if (rst) begin
      y_out <= 0;
      for(i=0;i<TAPS;i=i+1) xd[i] <= 0;
    end else begin
      xd[0] <= x_in;
      for(i=1;i<TAPS;i=i+1) xd[i] <= xd[i-1];
      y_out <= 0;
      for(i=0;i<TAPS;i=i+1) y_out <= y_out + $signed(h[i]) * $signed(xd[i]);
    end
  end
endmodule