FPGA Configuration Process

What actually happens between the moment you apply power and the moment the DONE pin goes high? This lesson walks through every stage of the FPGA configuration process — Power-On Reset, SRAM clearing, mode detection, bitstream loading, CRC verification, the startup sequence, and finally user mode. Understanding this sequence is essential for board bring-up, debugging boot failures, and implementing reliable field update strategies like MultiBoot.

Power-On Reset (POR)

The configuration process begins as soon as FPGA power supplies ramp up. The FPGA has an internal Power-On Reset (POR) circuit that monitors the core supply voltage (VCCINT). Until VCCINT crosses a minimum threshold and remains stable for a defined hold time, the POR circuit keeps the entire device in reset.

During POR:

• All configuration SRAM cells are cleared to 0 — all routing switches open, all LUTs set to output 0
• All IO pins are placed in a high-impedance, input-only state to avoid bus contention
• The INIT_B pin is driven low, signaling to external circuits that the FPGA is not yet ready
• The MODE pins M[2:0] are sampled and latched — the values must be stable before POR deasserts

When VCCINT is stable and the POR hold time expires, INIT_B rises to indicate the FPGA is ready to accept configuration data. On some boards an external circuit can hold INIT_B low longer than necessary (by driving it low externally) to delay configuration start — this can be useful for synchronizing multiple FPGAs.

Configuration Phase State Machine

The FPGA internal configuration controller implements a state machine with five sequential phases. Each phase must complete successfully before the next begins:

Startup Sequence Detail

The startup sequence is a programmable series of events controlled by the COR0 (Configuration Option Register 0). The key events and their order are:

• GTS release — Global Three-State release: IO output drivers become active. Before this event all FPGA IOs are high-impedance even though configuration is complete.
• GSR release — Global Set/Reset release: all flip-flops are released from their power-up reset state. The user design's flip-flops begin in a known state (set or reset according to their INIT attribute) and then begin clocking.
• EOS (End of Startup) — signals to the configuration controller that startup is complete.
• DONE assertion — DONE pin goes high. External circuits monitoring DONE know the FPGA is fully operational.

The startup clock source is configurable: JTAG clock (JTAGCLK), a user-provided clock (USERCLK2), or the internal configuration oscillator (CFGMCLK at ~65 MHz). The startup sequence typically completes within a few hundred nanoseconds after the last bitstream byte is loaded.

Master SPI Boot Sequence — Step by Step

Master SPI is the standard production boot mode. Here is the exact sequence of events from power-on to user mode:

Configuration Time by Device

Configuration time is determined by bitstream size divided by interface bandwidth. The table below shows theoretical loading times at the specified SPI clock rates. Real-world times may be slightly longer due to flash latency and protocol overhead:

JTAG Configuration

JTAG (IEEE 1149.1) is always available as a programming and debug interface regardless of MODE pin settings. The four JTAG signals are:

• TCK — Test Clock: clocks the JTAG state machine and data shift registers
• TMS — Test Mode Select: controls the JTAG state machine transitions
• TDI — Test Data In: serial data input to the device
• TDO — Test Data Out: serial data output from the device (captured on TDI edge)

In Vivado Hardware Manager: Open Target → Auto Connect → Program Device → select .bit file → Program. Multiple FPGA devices can be daisy-chained in a JTAG scan chain — TDO of device N connects to TDI of device N+1, sharing TCK and TMS. Vivado supports scan chains with up to 40+ devices. Recommended JTAG cables: Xilinx Platform Cable USB II or Digilent JTAG-SMT3-NC.

SelectMAP Configuration (CPU-Driven)

SelectMAP allows a host processor to push the bitstream to the FPGA over a parallel bus. This is the configuration method used in Zynq-7000 systems where the ARM Processing System (PS) programs the Programmable Logic (PL) after booting Linux or a bare-metal application.

• Bus width: 8, 16, or 32 bits. Wider buses dramatically reduce configuration time.
• Byte-wide SelectMAP bandwidth: at 100 MHz → 100 MB/s → XC7K325T loads in ~1.3 seconds
• 32-bit SelectMAP: theoretical 400 MB/s → XC7K325T in ~330 ms
• ICAP (Internal Configuration Access Port) — a dedicated primitive available in the FPGA fabric that allows the user design itself to write partial bitstreams to the FPGA configuration controller. Used for partial reconfiguration, MultiBoot management, and in-field design updates.

Configuration Error Recovery

If configuration fails — due to a corrupted bitstream, CRC mismatch, wrong bitstream for the device, or a noisy SPI bus — the FPGA indicates the error by reasserting INIT_B low. DONE will not go high. Recovery options:

• PROGRAM_B pulse — asserting PROGRAM_B low for at least 300 ns clears the configuration SRAM and restarts the entire configuration process from Phase 1. On production boards, this pin is often connected to a watchdog timer or supervisor IC.
• Watchdog supervisor — if DONE does not go high within a defined timeout (e.g., 5 seconds for a large device), the supervisor pulses PROGRAM_B to trigger a retry. After N retries, the supervisor can switch to a golden bitstream address.
• IPROG primitive — available from within running FPGA fabric, IPROG asserts PROGRAM_B internally and instructs the configuration controller to boot from a new address in SPI flash. Used to implement software-triggered reboot and MultiBoot.

MultiBoot / Golden Image Strategy

MultiBoot is Xilinx's mechanism for storing multiple bitstreams in SPI flash and automatically selecting between them based on boot success. Every production system handling field firmware updates should implement a MultiBoot scheme:

• Golden image — stored at SPI flash address 0. Contains a known-good, proven bitstream that should never be overwritten during field updates. The FPGA always boots from address 0 on power-on.
• Upgrade image — stored at a higher flash address (e.g., 0x400000). After verification, the golden image uses the WBSTAR (Warm Boot Start Address) register to redirect to the upgrade image address and triggers IPROG.
• Fallback mechanism — if the upgrade image fails (DONE does not go high within the POR timeout), the FPGA's internal MultiBoot watchdog automatically boots the golden image at address 0.
• Typical flash layout:

Knowledge Check

Practical Exercise