Introduction to FPGA
Understand what a Field-Programmable Gate Array is, where it came from, and why it is one of the most important technologies in modern electronics.
What Is an FPGA?
A Field-Programmable Gate Array (FPGA) is a semiconductor device containing a vast array of configurable logic blocks, programmable interconnect, and flexible I/O cells — all of which can be wired together in any configuration the designer chooses. Unlike a fixed-function chip (a microprocessor, an Ethernet controller, a GPU), an FPGA ships from the factory as a blank slate. The manufacturer creates the silicon with all the potential connections in place; the user then loads a bitstream — a binary configuration file — that programs millions of tiny SRAM cells to define exactly which logic evaluates which signals and which wires connect to which.
The result is a device that literally becomes a custom digital circuit. Every clock cycle, the logic fabric you defined computes your algorithm entirely in hardware, with no instruction-fetch overhead, no operating-system interrupts, and no pipeline stalls caused by branch misprediction. If you design a 256-tap FIR filter, the FPGA fabric IS that filter — 256 multipliers running in parallel every single clock cycle.
Modern FPGAs from AMD Xilinx (Versal, UltraScale+), Intel (Agilex), and Lattice (ECP5, Nexus) contain millions of logic cells, hundreds of megabits of on-chip RAM, thousands of DSP slices, high-speed serial transceivers at 100+ Gbps, and in the latest devices, hardened AI inference engines. They are far more than "programmable logic" — they are complete heterogeneous computing platforms in a single package.
A Brief History of FPGAs
The FPGA was invented by Ross Freeman and Bernard Vonderschmitt, who co-founded Xilinx in 1984. Freeman's key insight was that PLAs (Programmable Logic Arrays) could be extended into a much larger, more general architecture using SRAM cells to configure routing. The first commercial FPGA, the XC2064, appeared in 1985 and contained just 64 Configurable Logic Blocks (CLBs) and 58 I/O blocks — barely enough to implement a simple finite state machine.
FPGA Evolution at a Glance
FPGA Resource Growth Over Generations
The Three Fundamental Programmable Resources
Every FPGA, regardless of vendor or generation, is built around three foundational programmable resource categories. Understanding these is the foundation for everything else in this course.
Logic — LUTs and Flip-Flops
Lookup Tables (LUTs) implement any boolean function of N inputs by storing a truth table in SRAM. Flip-Flops register outputs for pipelined designs. Together they form the Configurable Logic Block (CLB) — the workhorse of every FPGA.
Routing — Programmable Interconnect
A hierarchy of programmable switch matrices and wire segments that can be configured to carry any signal to any destination on the chip. Routing accounts for 50–70% of FPGA silicon area and is often the critical path timing bottleneck.
I/O — Configurable IO Buffers
Programmable IO blocks (IOBs) implement hundreds of different voltage standards (LVCMOS, LVDS, SSTL) and drive strengths. High-speed serial transceivers (GTX, GTH, GTY) handle 10–112 Gbps per lane for PCIe, Ethernet, and optical interfaces.
A: An FPGA implements custom hardware logic in parallel — it IS the circuit. A microcontroller executes instructions sequentially in software on a fixed CPU core. The FPGA fabric has no instruction fetch cycle; every logic element evaluates every clock cycle simultaneously.
Industries That Rely on FPGAs
FPGAs appear in a remarkable diversity of industries, often hidden inside products you interact with daily. Their unique combination of high performance, reconfigurability, and longevity makes them irreplaceable in many applications.
| Industry | Key Applications | Why FPGA Wins | Example Device |
|---|---|---|---|
| Aerospace & Defense | Radar DSP, EW, satellite comms, radiation-hardened control | Rad-tolerant designs (RH FPGA families), long product life (20+ years), deterministic timing | Xilinx Virtex-5QV (space-grade) |
| Telecommunications | 5G base stations (fronthaul/midhaul), OTN switching, packet processing | Flexible protocol implementation, 400G+ line rate processing, low latency PHY | Xilinx UltraScale+ VU9P |
| Data Center | SmartNICs, network acceleration, ML inference, database offload | Programmable network pipelines, 100G/400G wire-rate processing, HBM bandwidth | Xilinx Alveo U55C, Versal AI Core |
| Automotive | ADAS sensor fusion, LiDAR processing, radar signal chain, ISO 26262 control | Functional safety (lockstep), real-time processing, sensor interface flexibility | Xilinx Zynq UltraScale+ MPSoC |
| Medical | Ultrasound beamforming, CT reconstruction, implantable device control, MRI | Ultra-low latency, custom ADC/DAC interfaces, FDA validation longevity | Xilinx Artix-7, Kintex-7 |
| Broadcast | 4K/8K video processing, SMPTE routing, real-time encode/decode | Multiple simultaneous video pipelines, standards agility (SDI, HDMI, NDI) | Xilinx UltraScale+ VU27P |
| Industrial | Motor control, machine vision, PLC I/O, real-time EtherCAT | Custom real-time control loops, microsecond response, custom fieldbus protocols | Xilinx Zynq-7000, Artix-7 |
| Financial (HFT) | Order management, market data feed processing, risk analytics | Sub-microsecond order-to-send latency, direct hardware I/O (QSFP), zero OS jitter | Xilinx Alveo U50, UltraScale+ VU13P |
Why FPGAs Matter More Than Ever
For decades, Moore's Law provided "free" performance — every two years, transistors halved in size and you got 2x the compute for the same power. That era is effectively over. At 5nm and below, each new node costs billions more to develop, delivers diminishing density gains, and faces fundamental physical limits. Designing a custom ASIC at cutting-edge nodes now requires NRE (Non-Recurring Engineering) costs of $50M–$500M.
FPGAs fill the gap perfectly. They are manufactured on the latest process nodes (TSMC 7nm for UltraScale+, TSMC 7nm for Versal) by AMD, meaning you get the transistor density and speed of leading silicon without paying NRE. You get hardware-level performance and energy efficiency, with the ability to change what the hardware does via a software bitstream update — at any time, anywhere in the world.
The rise of AI/ML workloads is the most recent driver. Neural network inference requires enormous arithmetic throughput but must run at the edge with tight power and latency budgets — a regime where FPGAs excel over both CPUs and GPUs. AMD's Versal AI Core with its AI Engine array demonstrates this convergence: programmable logic meets hardened neural network compute on the same die.
Knowledge Check
- Fully Programmable Gate Array
- Field-Programmable Gate Array
- Fixed-Program Generic Architecture
- Flexible Programmable Grid Array
- Gordon Moore (Intel)
- Jack Kilby (Texas Instruments)
- Ross Freeman (Xilinx)
- Andy Grove (Intel)
- Flash NOR memory
- EEPROM cells
- SRAM (Static RAM)
- Anti-fuse elements
- True — FPGAs use a fetch-decode-execute pipeline
- False — FPGAs evaluate all logic in parallel every clock cycle
- Programmable Logic (LUTs and Flip-Flops)
- Programmable Routing (Interconnect)
- Cache Memory (L1/L2 cache)
- Programmable I/O (IOBs)