Configurable Logic Blocks (CLB)

Understand the CLB — the fundamental repeating unit of FPGA logic fabric. Learn its internal structure, Slice contents, MUX hierarchy, and how RTL maps to physical CLB resources.

What is a CLB?

The Configurable Logic Block (CLB) is the fundamental repeating unit of FPGA programmable logic. Thousands to hundreds-of-thousands of CLBs tile the majority of the FPGA die area, forming a regular 2D array. Each CLB connects to the surrounding routing network through a local switch matrix, allowing signals to travel between CLBs and to dedicated resources (BRAM, DSP, IO).

In Xilinx 7-series, each CLB contains 2 Slices. The two Slices in a CLB share a switch matrix and are in close physical proximity, making intra-CLB routing fast and cheap. Adjacent CLBs are organized in columns and rows, with BRAM and DSP columns interspersed at regular intervals.

CLB Internal Structure

Xilinx 7-series CLB structure: 2 Slices, each with 4 LUT6s, 8 FFs, CARRY4, and MUX hierarchy

Slice Contents (7-Series)

Each Slice in a 7-series FPGA contains the following resources:

4× LUT6 — 6-input look-up tables (labeled A, B, C, D). Each implements any Boolean function of up to 6 variables. Can be split into two LUT5s for area efficiency.
8× Storage Elements — configurable as D flip-flops or transparent latches. Two per LUT (one after the LUT output, one can bypass the LUT). All share a common clock, CE, and SR signal per Slice.
1× CARRY4 — 4-bit fast carry chain for arithmetic. Connects vertically to CARRY4s in adjacent Slices above/below.
F7MUX — combines O6 outputs of two adjacent LUTs (A+B or C+D) to create a 7-input function or a 2:1 MUX with a 6-bit select.
F8MUX — combines the outputs of two F7MUXes (one from each LUT pair) to create an 8-input function or a 4:1 MUX.
Output MUXes — each LUT output can be taken directly (combinatorial) or registered (through the FF). The routing receives whichever the tool selects.

Signal Flow Through a Slice

graph LR IN[6 Inputs\nA1–A6 from routing] --> LUT6[LUT6\n64-bit memory\nany Boolean fn] LUT6 --> O6[O6 output] LUT6 --> O5[O5 output\nLUT5 split mode] O6 --> MUXF7[F7MUX\n7-input or 2:1 MUX] O6 --> OUTMUX[Output MUX\ndirect or registered] OUTMUX --> FF[D Flip-Flop\nCLK / CE / SR] OUTMUX --> DIRECT[Direct combinatorial\nto routing] FF --> Q[Q → routing network] CARRY4[CARRY4\nCin S O CO] --> FF MUXF7 --> F8MUX[F8MUX\n8-input function] F8MUX --> OUTMUX2[Output MUX\nregistered or direct]

The F7MUX and F8MUX — Wide Logic

A LUT6 can implement any 6-input Boolean function. But what if your HDL code needs a 7-input function, or a large CASE statement with many conditions? The F7MUX and F8MUX solve this efficiently:

F7MUX: Combines O6 outputs of two LUT6s. Input 7 (I6) selects which LUT output passes through. This implements any 7-input Boolean function, or a 2:1 MUX where select is one bit and data comes from the two LUTs.
F8MUX: Combines two F7MUX outputs. Implements 8-input functions or 4:1 MUXes. Used heavily for wide case statements (address decode, FSM next-state logic).

CLB Architecture — Generation Comparison

Feature	7-Series CLB	UltraScale CLB	UltraScale+ CLB
Slices per CLB	2	1	1
LUTs per Slice	4× LUT6	8× LUT6	8× LUT6
FFs per Slice	8	16	16
Carry chain per Slice	1× CARRY4 (4-bit)	1× CARRY8 (8-bit)	1× CARRY8 (8-bit)
Wide MUX	F7MUX, F8MUX	F7MUX, F8MUX, F9MUX	F7MUX, F8MUX, F9MUX
Distributed RAM	Slice M only	All Slices	All Slices
SRL	Slice M only	All Slices	All Slices
FF-to-LUT ratio	2:1	2:1	2:1

How RTL Logic Maps to CLB Resources

Vivado's synthesis engine automatically maps RTL to CLB primitives. Here are common examples:

RTL Construct	LUTs Used	FFs Used	CARRY4	Notes
4-input AND gate	1× LUT6	0	0	All 4 inputs fit in one LUT
8-input AND gate	2× LUT6 + F7MUX	0	0	Uses F7MUX to combine two LUTs
4-bit registered counter	4× LUT6	4	1	CARRY4 propagates carry
8-bit adder	2× CARRY4	0	2	Each CARRY4 handles 4 bits
16:1 MUX (4-bit data)	~8× LUT6	0	0	F7/F8MUX used for wide select
D flip-flop (no logic)	0	1	0	FF used standalone, LUT bypassed

Tool Reports Use "Slice LUTs", Not "CLBs" When Vivado reports resource utilization, it shows "Slice LUTs" (individual LUT6 primitives), "Slice Registers" (individual FFs), and "Slice" counts. It rarely reports CLB count directly. When you see "45,000 Slice LUTs used," that means 45,000 individual LUT6s — distributed across at most 45,000/4 = 11,250 Slices.

Engineering Tip: Balance LUT and FF Utilization If your design shows 85% LUT utilization but only 40% FF utilization, the design is logic-heavy and timing will be difficult. Add pipeline registers between logic stages to reduce the critical path and balance the ratio. Pipelining adds latency but dramatically improves maximum clock frequency and reduces routing congestion.

Interview Question: What is the F7MUX? Q: What is the F7MUX used for in a Xilinx 7-series Slice?
A: F7MUX combines the O6 outputs of two adjacent LUT6s to implement a 7-input Boolean function (where input 7 acts as the MUX select). This is critical for wide logic — large CASE statements in HDL, address decoders with 7+ address bits, and any function requiring more than 6 inputs. F8MUX extends this to 8 inputs by combining two F7MUX outputs.

Common Mistake: Slice Utilization vs LUT Utilization Vivado may show "60% Slice utilization" even when LUT utilization is 40%. A Slice is counted as "used" even if only 1 of its 4 LUTs is occupied. The tool tries to pack multiple logic functions into each Slice, but routing constraints can prevent tight packing. Always check BOTH "Slice LUTs" and "Slice" percentages to understand true resource pressure.

Knowledge Check

1. How many Slices are in one Xilinx 7-series CLB?

Correct! Each 7-series CLB = 2 Slices. In UltraScale/UltraScale+, each CLB = 1 Slice (with 8 LUTs per Slice instead of 4).

2. How many LUT6s are in one 7-series Slice?

Correct! Each 7-series Slice has 4 LUT6s (labeled A, B, C, D). UltraScale+ has 8 LUT6s per Slice.

3. How many flip-flops does each 7-series Slice provide?

A 4
B 8
C 16
D 2

Correct! 8 storage elements per 7-series Slice — 2 per LUT, all configurable as D flip-flops or transparent latches.

4. What is the primary purpose of the F7MUX in a Xilinx CLB?

A To merge carry signals from adjacent CARRY4 chains
B To implement 7-input Boolean functions by combining two LUT6 outputs
C To select between synchronous and asynchronous reset
D To route global clock signals into the Slice

Correct! F7MUX combines the O6 outputs of two LUT6s, creating a 7-input function (the 7th input is the MUX select). It is also used for wide data multiplexers in large CASE statements.

5. How many CARRY4 primitives are in one 7-series Slice?

A 1
B 2
C 4
D 0 — carry logic is in the LUT

Correct! One CARRY4 per Slice in 7-series. It handles 4-bit carry propagation using dedicated, fast wiring. Multiple CARRY4s cascade vertically between Slices for wider arithmetic.

Practical Exercise

Manual CLB Resource Mapping Estimate the CLB resources for each of the following designs, then verify by implementing in Vivado and checking the synthesis report:

A 2:1 MUX with 4-bit data buses (sel, a[3:0], b[3:0] → y[3:0])
A 4-input XOR gate (a, b, c, d → y)
A 3-bit synchronous up-counter with enable and synchronous reset

For each: predict LUT count, FF count, and CARRY4 usage. Compare your predictions to the Vivado synthesis report. If they differ, read the synthesis log to understand how the tool optimized the implementation.

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