Routing Architecture

Understand how signals travel between logic blocks in an FPGA — programmable switch matrices, wire segment types, and how the router places critical paths on fast resources.

The Routing Problem in FPGAs

In an ASIC, every wire is permanently etched into silicon during manufacturing. There is no ambiguity: signal A goes from block X to block Y via a fixed metal trace. The delays are determined by the physical wire length and can be precisely characterized.

In an FPGA, none of this is fixed at manufacture time. Every connection between logic blocks must be programmable. The FPGA contains a massive fabric of wire segments and programmable switches — the routing fabric — where SRAM bits control which switches are closed and which paths are active. When you load a bitstream, you are essentially programming millions of routing switches to form the wires your design needs.

The consequence of this programmability is that routing delay dominates FPGA timing. In most designs, 50–80% of the total path delay comes from routing — not from the LUTs, flip-flops, or other logic. Understanding the routing architecture is therefore essential for meeting timing in complex, high-frequency designs.

Routing Delay Dominates Routing delay represents 50–80% of total signal delay in most FPGA designs. A 4-input LUT may compute its function in 0.1 ns, but the signal routing from that LUT's output to the next LUT's input can easily take 0.5–2 ns depending on the wire segments chosen. The router's job is to pick the shortest available path for timing-critical signals.

Programmable Interconnect — The Switch Matrix

The routing fabric is organized as a two-dimensional grid. Each CLB sits at a grid intersection, surrounded by routing resources. Two types of structures connect everything together: the Connection Box (CB) and the Switch Box (SB).

Each routing switch is controlled by a single SRAM bit. When the SRAM bit is programmed to 1 (via the bitstream), the corresponding transistor switch closes and the wire segments connect. When it is 0, the switch is open. Each switch crossing adds approximately 0.1–0.3 ns of delay — which is why the number of routing hops on a path matters enormously for timing closure.

Wire Segment Hierarchy (7-Series)

Xilinx 7-series FPGAs provide multiple types of wire segments, each spanning a different number of CLBs. The router selects segment types based on the required distance and timing budget for each signal:

Segment Type	Span (CLBs)	Approx. Delay	Typical Use Case
Local	Within CLB	~0.05 ns	CLB-internal feedback between Slices
Single (SL1)	1 CLB	~0.1 ns	Adjacent CLB connections — tightest timing paths
Double (SL2)	2 CLBs	~0.2 ns	Local routing between nearby CLBs
Hex (SL6)	6 CLBs	~0.5 ns	Regional signals, medium-distance interconnect
Long	Span to device edge	~1–3 ns	Cross-chip routes, global reset/enable signals
Global (BUFG)	Full chip	Low skew	Clocks only — never for data signals

The router prefers SL1 and SL2 segments for timing-critical paths. When a design is congested or the logic is spread far apart, the router is forced to use Hex or Long segments — which is why placement quality directly determines timing quality. Logic that is placed far apart will always have longer routing delays.

Connection Box (CB) and Switch Box (SB) in Detail

Connection Box (CB): Connects the I/O pins of a CLB to the wire segments running horizontally and vertically beside the CLB.
Switch Box (SB): Connects wire segments to other wire segments at routing grid intersections.

Xilinx 7-series uses the Wilton switch box topology. In a Wilton SB, each incoming wire port connects to a specific subset of output ports — not all of them. This is intentional: a full crossbar would require too many SRAM bits and switches.

Routing Resources in Numbers

Metric	XC7A35T (Artix-7)	XC7K325T (Kintex-7)
CLBs	5,200	50,950
Routing SRAM bits (approx.)	~81,000	~800,000
Routing bits as % of bitstream	~60–70%	~60–70%
SL1 delay	~0.1 ns	~0.1 ns
SL6 delay	~0.5 ns	~0.5 ns
Long segment delay	1–3 ns	1–3 ns

Routing Congestion

Routing congestion occurs when too many signals compete for the same wire segments in a region of the FPGA. Solutions: Pblock constraints, floorplanning, reduced design density, phys_opt_design, pipeline registers.

Critical Path Routing Analysis

                # Run this after implementation to see per-segment routing delay breakdown
                report_timing -max_paths 10 -path_type full -datasheet # Example timing path output
                (simplified): # Source: FF_A/C (FF output) Delay: 0.10 ns (FF clock-to-output) #
                Net: ff_a_to_lut_b # SL1 segment (adjacent CLB) Delay: 0.11 ns <-- fast routing #
                Destination LUT input Delay: 0.05 ns # Total: 0.26 ns # # Versus a poorly placed
                path: # Source: FF_A/C Delay: 0.10 ns # Net: ff_a_to_distant_lut # SL6 segment
                Delay: 0.52 ns # SB crossing Delay: 0.18 ns # SL2 segment Delay: 0.21 ns #
                Destination LUT input Delay: 0.05 ns # Total: 1.06 ns <-- 4x worse due to
                routing, not logic
              

Inspect Routing in Vivado Device View Open an implemented design in Vivado and use the Device view colored by routing utilization (View → Color Scheme → Routing). High-utilization tiles appear red/orange — these are your congestion hotspots.

Never Route Clocks Through General Fabric Clock signals must never be routed through general routing fabric. Always route clocks through BUFG or BUFH buffers, which drive the dedicated H-tree clock distribution network with <100 ps skew.

Multi-Die Routing — UltraScale+ SSI Devices

UltraScale+ SSI devices use multiple dice on a passive silicon interposer connected via Super Long Lines (SLL). Each SLL crossing adds ~1.5–2 ns. Group related logic into the same SLR and register signals at every inter-die boundary.

Routing Type	Delay	Constraint
Within-SLR routing (SL1)	~0.1 ns	No special constraint needed
Within-SLR routing (SL6)	~0.5 ns	No special constraint needed
Cross-SLR via SLL	~1.5–2.0 ns	Must be registered — pipeline across boundary

Interview Question Q: What is the difference between a Connection Box and a Switch Box in FPGA routing?

A: A Connection Box (CB) connects CLB I/O pins to the wire segments running alongside the CLB — it is the interface between logic and the routing grid. A Switch Box (SB) connects wire segments to other wire segments at grid intersections, forming the programmable routing mesh.

Knowledge Check

1. What percentage of total signal delay in a typical FPGA design comes from routing (not logic)?

A 10–20%
B 30–40%
C 50–80%
D 90–95%

Correct! Routing delay accounts for 50–80% of total signal delay in most FPGA designs.

2. Which wire segment type spans 6 CLBs in Xilinx 7-series routing architecture?

A Single (SL1)
B Double (SL2)
C Hex (SL6)
D Long

Correct! Hex (SL6) segments span 6 CLBs and add approximately 0.5 ns of delay.

3. What routing structure connects CLB I/O pins to wire segments in the FPGA routing grid?

A Connection Box (CB)
B Switch Box (SB)
C BUFG buffer
D Super Long Line (SLL)

Correct! The Connection Box (CB) is the interface between a CLB and the routing grid.

4. What is routing congestion in an FPGA?

A Too many LUTs used in one CLB region
B Too many signals competing for the same wire segments in a region
C A clock signal routed through general fabric instead of BUFG
D Too many CARRY4 primitives in a single column

Correct! Routing congestion occurs when the router cannot find uncongested wire segments in a region.

5. In UltraScale+ SSI (multi-die) FPGAs, what connects different dice (SLRs) to each other?

A Long wire segments through general routing
B BUFG clock buffers
C Super Long Lines (SLL) on the silicon interposer
D PCIe lanes built into the FPGA

Correct! Super Long Lines (SLL) are dedicated wires on the passive silicon interposer that connect the SLRs.

6. Which Vivado Tcl command shows the detailed per-segment routing delay breakdown for a timing path?

A report_utilization
B report_congestion
C report_timing
D report_route_status

Correct! report_timing -max_paths 10 -path_type full shows a complete breakdown of each timing path.

Summary

FPGA routing is programmable — SRAM bits control which wire segments and switches are active
Routing delay accounts for 50–80% of total signal delay in most FPGA designs
Connection Boxes (CB) connect CLB pins to wire segments; Switch Boxes (SB) connect wire segments to each other
Wire segment hierarchy (7-series): Local → SL1 (0.1 ns) → SL2 (0.2 ns) → SL6 (0.5 ns) → Long (1–3 ns)
Routing congestion is solved with Pblocks, floorplanning, and reduced density
Use report_timing -path_type full to see per-segment routing delays
UltraScale+ SSI: SLR-to-SLR crossings via SLL cost ~1.5–2 ns — minimize inter-die crossings
Never route clocks through general fabric — always use BUFG or BUFH for <100 ps skew