FPGA Academy 25 Lessons AMD Xilinx Beginner → Advanced

FPGA Fundamentals
& Architecture

A complete industry-grade FPGA course — from "what is an FPGA?" to deep-diving into AMD Xilinx CLBs, LUTs, DSP slices, transceivers, and the full design flow. Taught from the perspective of a Senior FPGA Architect with 25+ years of industry experience.

25
Lessons
12h+
Learning Time
125+
Quiz Questions
Start Learning View Summary & Cheat Sheet

Core Lessons

25 self-contained lessons. Each builds on the previous — complete them in order for best results.

01
Introduction to FPGA
What is an FPGA? History, evolution, why FPGAs exist, and which industries rely on them.
Lesson10–15 min
02
Why FPGA?
Flexibility, reconfigurability, parallel processing, low latency, and hardware acceleration advantages.
Lesson10 min
03
FPGA vs MCU
Architecture, execution, performance, memory, and power — a full interactive comparison.
Lesson12 min
04
FPGA vs ASIC
NRE costs, performance, power, volume economics, time to market, and risk tradeoffs.
Lesson15 min
05
FPGA vs GPU
Parallelism, latency, throughput, AI/DSP acceleration — when to choose which.
Lesson12 min
06
AMD Xilinx FPGA Families
Spartan, Artix, Kintex, Virtex, Zynq, Versal — architecture, use cases, and comparison tables.
Lesson15 min
07
Inside an FPGA Chip
Silicon die, packaging, IO banks, clock network, and configuration memory — annotated diagrams.
Lesson12 min
08
FPGA Internal Architecture Overview
CLB, Slice, LUT, FF, Routing, Switch Matrix, BRAM, DSP, Clock — the full picture.
Lesson20 min
09
Configurable Logic Blocks (CLB)
Structure, components, and how CLBs implement arbitrary digital logic.
Lesson12 min
10
Slices — Slice L & Slice M
Differences between Slice L and Slice M, their capabilities, and design implications.
Lesson10 min
11
Lookup Tables (LUT)
Truth tables, boolean implementation, 6-input LUTs — interactive examples.
Lesson15 min
12
Flip-Flops & Registers
D flip-flop, setup/hold timing, clock-to-Q, metastability, and pipeline registers.
Lesson15 min
13
Carry Chains
Fast arithmetic via dedicated carry logic — adders, subtractors, counters, comparators.
Lesson10 min
14
Routing Architecture
Programmable interconnect, switch matrix, wire segments, and timing implications.
Lesson15 min
15
Clock Distribution Network
Global clocks, BUFG, BUFH, MMCM, PLL — clock skew, jitter, and management.
Lesson18 min
16
Block RAM (BRAM)
Organization, dual-port operation, initialization, ECC, FIFO mode.
Lesson15 min
17
Distributed RAM
LUT-based RAM, advantages over BRAM for small memories, shift register mode.
Lesson10 min
18
DSP Slices
Pre-adder, multiplier, accumulator (MAC), FIR filters, AI inference, signal processing.
Lesson18 min
19
IO Banks & Standards
Voltage standards, LVTTL, LVCMOS, LVDS, differential IO, drive strength.
Lesson15 min
20
High-Speed Transceivers
GTX, GTH, GTY transceivers — PCIe, Ethernet, Aurora, 100G serial links.
Lesson18 min
21
Configuration Memory
Bitstream format, SRAM configuration cells, external flash, configuration modes.
Lesson12 min
22
FPGA Configuration Process
Power-on sequence, configuration modes (JTAG, SPI, BPI, SelectMAP), partial reconfig.
Lesson12 min
23
FPGA Development Flow
RTL → Simulation → Synthesis → Implementation → Timing Closure → Programming → Debug.
Lesson20 min
24
Complete Architecture Walkthrough
A guided tour combining all previous lessons into one unified architectural view.
Lesson20 min
25
Course Summary, Cheat Sheet & Mini Project
Key takeaways, architecture poster, 50-question quiz, interview Q&A, and mini project.
Capstone30 min

Prerequisites

This course starts from absolute basics. You will benefit from:

Basic digital logic (AND, OR, FF)
Ohm's Law and basic circuits
Some programming experience
PCB concepts (helpful, not required)