Capstone Bridge / Mini-Project
Everything from Modules 01–11 comes together here in one design exercise — then hands off to the site's existing DDR4 SI verification capstone, which picks up exactly where this course leaves off.
Where this capstone sits
This mini-project asks you to make and justify the same decisions a real design would require, using Modules 01–11 as your reference. It ends with a bridge into the DDR4 SI verification capstone, which assumes an interface like the one you just designed and walks through post-layout simulation, eye-diagram analysis, and sign-off.
Mini-project brief
Scenario: you're designing a DDR4-2400 interface between a mid-range FPGA (hardened memory PHY) and a single-rank, x16, discrete DDR4 DRAM, targeting an embedded vision/compute board. Work through the tasks below in order — each one leans directly on a specific module.
Reveal self-check answer key
| Task | Expected answer |
|---|---|
| 1 | Timing table, electrical characteristics, IDD current tables, package/ball map; cross-check FPGA controller's max supported speed grade and DCI/OCT support. |
| 2 | DDR4-2400: tCK ≈ 0.833 ns; typical CL17 → tRCD/tRP ≈ 13.32 ns ÷ 0.833 ns ≈ 16 cycles. |
| 3 | Fly-by, daisy-chained in device order, for CA/CK/control; point-to-point per byte lane for DQ/DQS (single device, so trivially point-to-point). |
| 4 | Two byte lanes (x16 = 2 × x8); each lane = DQ[7:0] + DQS/DQS# + DM/DBI. |
| 5 | VTT termination at the true end of the CA fly-by bus; RTT_NOM enabled at idle, RTT_WR (or off) during writes, per datasheet defaults. |
| 6 | Bulk (~100–220 µF) near the regulator; 1 µF mid MLCC ringing FPGA/DRAM power pins; 0.1/0.01 µF MLCC as close to each power ball as possible. |
| 7 | DQS+/DQS− tightest, then DQ/DM to DQS within a lane, then byte-lane-to-byte-lane, then CA/CK looser but still bounded. |
| 8 | DQ bits within the lane are freely swappable; DQS and CK pins are fixed to the hardened PHY lane. |
Next: verify what you just designed
This course stops at a routed board. The natural next step is verification — taking that routed interface through post-layout simulation, checking eye diagrams against the JEDEC mask, and producing a sign-off report before bring-up. That's exactly what the site's existing DDR4 SI capstone covers.