Module 05 Diagrams

Signal Groups & Their Roles

Every DDR4 pin belongs to one of a handful of functional groups. Knowing which group a signal belongs to tells you immediately how it should be routed, terminated, and matched — which is exactly why this grouping recurs throughout the rest of the course.

The full signal map

Diagram
DDR4 DRAM CK / CK# (clock) CA / Address (RAS/CAS/WE, bank) Control CS / CKE / ODT / RESET# DQ[7:0] (data) DQS / DQS# + DM/DBI VREF / ZQ reference & cal.
Clock — differential, fly-by
Command/Address — single-ended, fly-by
Control — single-ended, fly-by
Data (DQ) — single-ended, point-to-point per lane
Data strobe — differential, point-to-point per lane
VREF/ZQ — reference & calibration, not switching data

Signal-by-signal reference

Signal Type Role
CK / CK# Differential System clock the DRAM samples every other signal against.
CS (chip select) Single-ended Selects which rank/device a command targets.
RAS# / CAS# / WE# (or ACT_n + address, DDR4 encoding) Single-ended Encode the command type (ACTIVATE, READ, WRITE, PRECHARGE, REFRESH…).
Address (A[13:0], BA/BG) Single-ended Row/column address plus bank and bank-group select.
CKE (clock enable) Single-ended Gates the clock for power-down/self-refresh states.
ODT (on-die termination control) Single-ended Tells the DRAM when to enable its internal termination (Module 07).
RESET# Single-ended Power-up/hard reset of the device.
DQ[7:0] per byte Single-ended The actual data bus — 8 bits per byte lane.
DQS / DQS# per byte Differential Source-synchronous strobe the controller/DRAM uses to sample DQ.
DM / DBI per byte Single-ended Data mask (write byte enables) or, when configured, data-bus inversion for SI.
VREF (DQ and CA, separate pins on DDR4) Reference Receiver decision threshold (Module 03).
ZQ Reference Precision resistor input the DRAM uses to calibrate its own output driver and ODT impedance.

The byte-lane grouping concept

Diagram

DQ[7:0], DQS/DQS#, and DM/DBI for a given byte are not independent signals — they are sampled relative to each other and must be treated as a single routing/matching unit. This "byte lane" concept is the single most important idea for Module 09's length-matching rules.

Byte Lane 0 — one matched group DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS / DQS# DM / DBI All 10 signals here get the same tight length-matching tolerance (Module 09)
A x8 DRAM has one byte lane; a x16 device has two; the FPGA memory interface mirrors this same grouping on its I/O banks (Module 10) — pin-swap rules almost always respect byte-lane boundaries.

Differential vs. single-ended handling

CK, DQS (differential) CA, DQ, control (single-ended)
Reference Complementary pair — each compares against the other Compares against VREF
Noise immunity Higher — common-mode noise cancels Lower — sensitive to VREF noise (Module 08)
Routing rule Tightly length- and impedance-matched pair (Module 09) Matched to the group's budget, referenced to VREF

Key takeaways

  • Six functional groups cover the whole interface: clock, command/address, control, data, data strobe, and reference/calibration (VREF, ZQ).
  • Clock, CA and control are shared fly-by signals; DQ/DQS/DM are point-to-point per byte lane.
  • A byte lane (DQ[7:0] + DQS/DQS# + DM/DBI) is the fundamental routing/matching unit for Module 09.
  • Differential signals (CK, DQS) get their noise immunity from the complementary pair; single-ended signals depend entirely on a clean VREF.
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