Module 09 Diagrams Checklist

Layout & Routing Guidelines

Everything from Modules 05–08 — signal groups, SI, termination, and the PDN — converges into one set of concrete PCB rules here. This is the module where the schematic becomes a board.

The length-matching hierarchy

Not every signal needs the same tolerance. DDR4 length matching is nested — tightest within a byte lane, looser between byte lanes, looser still against the shared command/address bus.

Match group Typical tolerance Why
DQS+/DQS− (intra-pair) ± 2–5 mil Differential pair skew directly degrades the strobe edge
DQ[7:0] + DM/DBI to their DQS (intra-byte-lane) ± 10–25 mil (per vendor guide) Sets read/write data-valid window inside that lane
Byte lane to byte lane Looser, but bounded (per vendor guide) Read leveling/deskew has real but finite range
CK+/CK− (intra-pair) ± 2–5 mil Clock pair skew shows up on every sampled bit
CA/address/control (fly-by group) Looser than DQS, still bounded Write leveling compensates CK-to-DQS skew, not CA skew
Always route to the exact tolerances in your specific FPGA vendor's memory interface routing guidelines (Module 10) — the numbers above are typical orders of magnitude, not a substitute for the datasheet.

Length matching in practice: serpentine tuning

Diagram
DQ0 (short, direct route) DQ1 (physically shorter path — needs length added) serpentine (accordion) meander adds exactly the missing length

Both traces now carry the same electrical delay end-to-end, even though DQ1's direct path was physically shorter — the meander adds length, not just distance on the page.

Keep serpentine spacing at least 3–4× the trace width apart to avoid the meander itself becoming a crosstalk source between adjacent turns (Module 06).

Reference planes & impedance control

Diagram
L1 — DDR signal layer (microstrip) L2 — solid GND reference (uninterrupted under DDR signals) L3 — VDDQ / power plane L4+ — additional signal/plane layers Avoid routing DDR signals across any plane split crossing this boundary

A continuous, uninterrupted reference plane directly adjacent to the signal layer is what makes the trace's impedance predictable in the first place — a signal that crosses a plane split loses its return path and effectively creates a large, unplanned impedance discontinuity (Module 06).

Via & stub minimization

  • Minimize layer changes on critical DQ/DQS/CK nets — every via adds inductance and a potential stub.
  • Back-drill or use blind/buried vias on higher-layer-count boards to remove the unused portion of a through-hole via barrel.
  • Keep a ground via next to every signal via changing layers, to preserve a short return path (mirrors the PDN loop-area lesson from Module 08).
  • Route an entire byte lane's vias at the same board location where practical, so lane members see similar via-induced delay and impedance effects.

Fly-by routing order

Module 04 established that CA/CK/control must daisy-chain past each device in order, never branch. The routing consequence: keep every address/command/control line in the same physical device order down the bus, and terminate only after the last device — reordering even one line creates its own hidden skew that write/read leveling wasn't designed to correct.

Group the whole CA/CK fly-by bundle in the routing tool as one ordered unit before you start pulling traces — reordering later, after other nets are already routed around it, is one of the most time-consuming DDR4 layout mistakes to fix.

Differential pair routing rules (CK, DQS)

Rule Typical guidance
Intra-pair length match ± 2–5 mil, matched as close to the discontinuity as possible
Coupling spacing Tight and consistent for the full run — don't let spacing drift
Layer changes Change both traces of a pair together, same via pattern
Reference plane Same continuous reference for both traces of the pair, full length

Routing checklist

  • CA/CK/control routed as one ordered fly-by bundle, no branching
  • DQ/DQS/DM grouped and length-matched per byte lane
  • Differential pairs (CK, DQS) intra-pair matched and consistently coupled
  • Continuous reference plane under every DDR signal layer, no plane-split crossings
  • Via count minimized on critical nets; stubs back-drilled where applicable
  • VTT termination placed at the true electrical end of the CA fly-by bus
  • Decoupling caps placed with shortest possible loop to each power ball (Module 08)
  • Final lengths verified against the FPGA vendor's memory-interface routing guide (Module 10)

Key takeaways

  • Length-matching tolerance is nested: tightest inside a byte lane, looser between byte lanes, looser still on the shared CA/CK bus.
  • Serpentine meanders add electrical length without changing endpoints — spacing them properly avoids self-crosstalk.
  • A continuous reference plane under every DDR signal layer is what makes trace impedance predictable in the first place.
  • Fly-by nets must stay in the same device order throughout routing — reordering breaks an assumption leveling can't fix.
  • Differential pairs need matched, consistent coupling and layer changes performed together, not independently.
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