Module 03 Plotly

Key Electrical & Timing Parameters

Every DDR4 datasheet is dominated by a dense timing table and an electrical characteristics section. This module turns that alphabet soup — tCK, CL, tRCD, tRP, tRAS, tRFC and friends — into a mental model you can actually reason with.

The command cycle these parameters describe

Animated

Almost every timing parameter measures a gap between two commands on the same bank: ACTIVATE opens a row, READ/WRITE accesses it, PRECHARGE closes it before a different row can open.

ACT open row READ access row PRE close row ACT new row tRCD tRAS (min row-open time) tRP

tRCD (ACT→READ/WRITE), tRAS (ACT→PRE minimum) and tRP (PRE→next ACT) chained together give tRC — the minimum time between two ACTIVATEs on the same bank.

JEDEC timing parameter glossary

Parameter Meaning
tCK Clock period — the base unit almost every other parameter is expressed in cycles of.
CL (CAS latency) Cycles from READ command to first data out. The number printed in "DDR4-3200 CL22" style names.
tRCD ACTIVATE → READ/WRITE minimum delay (row must be open before accessing it).
tRP PRECHARGE → next ACTIVATE minimum delay (row must fully close before reopening).
tRAS Minimum time a row must stay open (ACTIVATE → PRECHARGE).
tRC Minimum ACTIVATE-to-ACTIVATE time on the same bank = tRAS + tRP.
tRFC Refresh cycle time — how long a REFRESH command blocks the bank; grows with density.
tFAW Four-Activate Window — limits how many ACTIVATEs can happen in a rolling window (controls peak current).
tWTR Write-to-read turnaround — bus direction change penalty.
tRRD Minimum time between ACTIVATEs on different banks.
tCCD Minimum time between two column commands (back-to-back READs/WRITEs).
ODT On-die termination setting — which internal resistance the DQ/DQS receiver presents (Module 07).
RON (drive strength) Output driver impedance setting — pairs with ODT to set the effective line impedance.
Slew rate How fast the output transitions — faster edges mean tighter SI budgets (Module 06).
Datasheets usually give timing parameters in both nanoseconds and clock cycles. The ns value is what physically matters; the cycle count is what the controller actually programs. Module 03's chart below shows why both views matter.

Interactive: the same latency, three speed grades

Plotly

tRCD stays roughly 13–14 ns across DDR4 speed grades — but because the clock period shrinks as data rate rises, that same real-world delay costs more and more clock cycles. This is why doubling the data rate doesn't double your effective bandwidth for latency-sensitive access patterns.

tRCD expressed in nanoseconds (flat, left axis) vs. clock cycles (rising, right axis) across three DDR4 speed grades.

I/O standards & VREF

Generation I/O standard Nominal swing
DDR3 SSTL-15 1.5 V, VREF ≈ VDDQ/2
DDR4 SSTL-135 / POD12 1.2 V, VREF ≈ VDDQ/2
DDR5 POD (decision-feedback assisted) 1.1 V, per-pin DFE
LPDDR4/5 Low-swing single-ended 1.1 V / 0.5 V

VREF is the receiver's decision threshold — every DQ/CA input compares the incoming signal against it to decide 0 vs. 1. Because VREF sits at roughly the midpoint of the signal swing, any noise on VREF directly eats into your read/write margins exactly like noise on the signal itself — which is why Module 08 treats VREF decoupling as seriously as the main power rails.

A preview: why leveling exists

At DDR4 speeds, the propagation delay difference between the first and last DRAM on a fly-by bus (Module 04) is a meaningful fraction of a bit period. Rather than fight this purely with layout, the controller runs a read/write leveling calibration at power-up: it measures the actual delay to each device and adjusts its own timing per byte lane to compensate. Your layout's job (Modules 04, 09) is to keep that delay within the range leveling can correct — not to eliminate it entirely.

Key takeaways

  • Most timing parameters measure gaps around ACTIVATE/READ-WRITE/PRECHARGE on a bank; tRC = tRAS + tRP ties them together.
  • Parameters are fixed in nanoseconds by the silicon but cost more clock cycles as speed grade rises.
  • SSTL/POD I/O standards center around a VREF threshold — VREF noise is just as damaging as signal noise.
  • Read/write leveling exists specifically to correct fly-by propagation delay differences your layout can't fully eliminate.
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