Module 01

Introduction & the DDR Landscape

Memory-interface design is one of the least forgiving parts of a board: hundreds of megabits per second per pin, dense BGA breakout, and a timing budget measured in picoseconds. This module maps the territory — which DDR generation to reach for, what your FPGA actually gives you, and where this design course fits in your overall project flow.

Why this interface is uniquely hard

Most interfaces on a board tolerate sloppy layout. DDR does not, for three reasons that this course keeps coming back to:

  • Speed. DDR4-3200 toggles data at 3200 MT/s — a bit period of just 312.5 ps. A few hundred picoseconds of uncontrolled skew is the entire margin budget.
  • Pin density. A x72 (ECC) DDR4 interface is well over 150 signal pins on both the FPGA and the DRAM devices, almost all in fine-pitch BGA packages — breakout alone is a real routing challenge (Module 09).
  • It's a bus, not a link. Multiple DRAM devices share the same command/address/clock lines (Module 04), so topology and length-matching choices affect every device at once.
The payoff for getting it right: DDR is by far the cheapest way to get gigabytes of fast, byte-addressable memory next to your FPGA. There's no shortcut around learning to design the interface properly.

The DDR generation landscape

Five memory families cover almost every FPGA project you'll meet. Module 02 turns this into a decision matrix with an actual recommendation; for now, get the shape of each one:

Family Typical data rate I/O voltage Topology norm Where it's used
DDR3 800–1866 MT/s 1.5 V (1.35 V DDR3L) Fly-by, VTT termination Cost-sensitive / legacy designs, mature tool support
DDR4 1600–3200 MT/s 1.2 V Fly-by, on-die + VTT-light Mainstream FPGA memory today — this course's primary focus
DDR5 3200–6400+ MT/s 1.1 V Fly-by, on-die decision-feedback Newest high-bandwidth designs; fewer FPGA families support it yet
LPDDR4/4x 1600–4266 MT/s 1.1 V (VDDQ), low power Point-to-point (Module 04) Mobile, battery, thermally-constrained boards
LPDDR5 up to 6400+ MT/s 0.5 V (VDDQ) Point-to-point High-bandwidth low-power (edge AI, handhelds)
This course uses DDR4 as the running example throughout — it's still the most common choice for new FPGA designs — but every principle (topology, signal groups, SI, termination, decoupling, routing) transfers directly to DDR3/DDR5, with LPDDR simplifying several of them (flagged as we go).

The FPGA-specific angle: hard vs. soft controller

Unlike a fixed SoC with one memory controller, an FPGA's memory interface capability depends entirely on the silicon family you picked:

Hard memory controller / PHY Soft (fabric-based) controller
Max speed Highest the family supports (often 3200+ MT/s) Lower — fabric timing becomes the limit
Fabric resources Minimal — controller is dedicated silicon Consumes LUTs/FFs/PLLs you might want elsewhere
Design effort Configure via vendor wizard (Module 10) More manual timing closure work
Typical use Default choice whenever the family has one Smaller/cheaper FPGAs without a hard controller

Either way, the board design problem — this course — barely changes: the DRAM side doesn't know or care whether the controller is hard or soft. What changes is which pins on the FPGA are eligible for which DDR signal, covered in Module 10.

Where this course fits

Rising Edge's Signal Integrity Academy already has a DDR4 SI Verification capstone — but it starts from an assumption: the interface already exists on a board. This course is the missing piece before that: how to actually design it.

Select components
→
Design (this course)
→
Route the board
→
Verify (SI capstone)
→
Bring-up

Module 12 hands you off explicitly into that capstone with a concrete mini-project brief.

What you're actually wiring together

An FPGA development board with the FPGA package and surrounding memory/support circuitry visible

An FPGA board — the memory controller lives inside the large FPGA package; DRAM devices sit nearby, connected by the fly-by topology covered in Module 04. Source: Wikimedia Commons.

Key takeaways

  • DDR4 is the mainstream FPGA memory choice today; DDR3/DDR5/LPDDR4-5 trade cost, bandwidth and power differently — Module 02 gives you a decision matrix.
  • Speed, pin density and shared-bus topology are what make DDR interfaces unforgiving to lay out — every later module traces back to one of these three.
  • Hard vs. soft memory controller changes fabric resources and achievable speed, but barely changes the board-design problem this course covers.
  • This course designs the interface; the existing SI Academy DDR4 capstone verifies it. Together they cover the full lifecycle.
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