Module 08 Plotly

Decoupling & Power Delivery Network (PDN)

Module 06 mentioned simultaneous switching noise — this module is where you design the fix. A DDR4 interface's power rail needs to look like a very low impedance source from DC up through several hundred MHz, all at once.

Target impedance: the PDN's one design spec

Every capacitor placement decision traces back to a single target:

Z_target = ΔV / ΔI
Allowed ripple ÷ transient current
~20–50 mΩ
Typical DDR4 VDDQ target
DC → ~500 MHz
Frequency range that must stay under target

No single capacitor covers that whole range — a voltage regulator handles low frequencies, bulk capacitors cover the mid-band, MLCCs cover the upper-mid band, and plane capacitance takes over above a few hundred MHz.

Interactive: build a decoupling stack and watch impedance vs. frequency

Plotly

The stack below combines a bulk capacitor bank with two MLCC values. Try lowering the MLCC count or raising mount inductance (poor placement / long via) and watch the impedance curve rise above the target line — especially the "anti-resonance" peak where the bulk and MLCC ranges hand off to each other.

Fewer MLCCs or longer via/pad loops (higher mount inductance) both push the curve upward and widen the anti-resonance peak — the two levers layout actually controls, versus capacitor selection which controls the flat regions on either side.

The decoupling stack, layer by layer

Stage Typical value Covers Placement
VRM / regulator loop — DC – ~100 kHz Regulator feedback & bulk output caps
Bulk capacitors 47–330 µF (polymer/tantalum) ~100 kHz – few MHz Near the regulator and spread across the board
Mid MLCC 1 µF, 2.2 µF Few MHz – tens of MHz Ringed around FPGA/DRAM power pins
High-frequency MLCC 0.1 µF, 0.01 µF Tens – hundreds of MHz As close to each power ball as physically possible
Plane capacitance Inherent to power/ground plane pair Hundreds of MHz and up Tight plane spacing, no discrete part needed

Why placement matters as much as capacitor value

Good: short loop, low ESL BGA ball cap directly under/adjacent Poor: long loop, high ESL BGA ball cap routed far away via long trace
Loop area (not just via count) drives mount inductance — a cap with a short, wide return path to the adjacent ground via beats a "closer on paper" cap with a long thin trace detour.

Key takeaways

  • The PDN has one governing spec — target impedance = allowed ripple ÷ transient current — that must hold from DC through several hundred MHz.
  • No single capacitor covers that range; a bulk/mid-MLCC/high-frequency-MLCC/plane-capacitance stack covers different frequency bands together.
  • Mount inductance (via + pad loop geometry), not just capacitor value, sets how well a cap performs at high frequency.
  • Too few high-frequency MLCCs or long return loops create an anti-resonance peak that can push impedance above target right where DDR4 switching noise lives.
  • This module and Module 06 (SI) both point to the same root cause — simultaneous switching noise — from two different design levers.
← Termination Strategies Next: Layout & Routing →