Module 07 Plotly

Termination Strategies

Module 06 showed what an unterminated discontinuity does to the eye. Termination is the fix: absorb the energy that would otherwise reflect, at the point in the circuit where it does the least harm.

The reflection coefficient, in one number

Plotly

Every termination decision comes back to one relationship: how close the termination resistance Rt is to the line's characteristic impedance Z0 (typically 40–50 Ω single-ended, ~85–100 Ω differential for DDR4). The reflection coefficient Γ = (Rt − Z0) / (Rt + Z0) tells you what fraction of the signal bounces back.

Notice Γ = 0 only when Rt = Z0 exactly. A "perfect" 50 Ω termination on a 40 Ω trace still reflects roughly 11% of the signal — impedance control (Module 09) and termination selection have to agree with each other.

Four termination strategies, side by side

Series (source) termination

FPGA Rs DRAM

Small resistor at the driver, sized so Rs + driver output impedance ≈ Z0. Common on point-to-point DQ/DQS from an FPGA when the on-die driver alone doesn't match the line.

Parallel / Thevenin (VTT) termination

Driver Rtt VTT

Resistor(s) to a VTT rail (~VDDQ/2) at the far end of the fly-by bus. Used for the shared CA/CK/control lines, since a discrete DRAM has no on-die termination for those pins.

On-die termination (ODT)

FPGA DRAM RTT (internal)

DQ/DQS/DM pins terminate inside the DRAM package itself, switched dynamically between RTT_nom (idle), RTT_wr (writes) and RTT_park — no board-level resistor needed.

Differential termination

~100Ω

A single resistor across the receiving end of CK/CK# or DQS/DQS# matches the pair's differential impedance directly — simplest and most effective termination in the whole interface.

DDR4 ODT modes (data pins)

Mode When active Typical value range
RTT_NOM Default/idle termination while not being written to 34–120 Ω
RTT_WR Enabled during writes to that rank 60–240 Ω, or off
RTT_PARK Value parked when ODT would otherwise be disabled Device/JEDEC defined

These values are set by the FPGA memory controller through mode-register writes during initialization — matching them to your topology (Module 04) and trace impedance (Module 09) is normally handled by the memory-interface IP's timing/SI wizard, but knowing what the numbers mean is essential for debugging bring-up issues (Module 11).

A fly-by CA bus with no VTT termination at its far end is the classic "it never calibrates" symptom in a first DDR4 board bring-up — the open end reflects nearly 100% of the signal back down the bus.

Key takeaways

  • Termination absorbs the energy that Module 06's reflections would otherwise bounce back — the goal is always Rt ≈ Z0.
  • Series termination lives at the driver; parallel/Thevenin (VTT) termination lives at the far end of the shared fly-by CA bus.
  • DDR4 data pins terminate on-die (ODT) with dynamically switched RTT_nom/RTT_wr/RTT_park — no board resistor required for DQ/DQS/DM.
  • Differential termination is a single resistor across CK/CK# or DQS/DQS# at the receiver, matched to the pair's differential impedance.
  • An unterminated fly-by CA bus is one of the most common causes of a board that fails to train at power-up.
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