Module 10 Diagrams

FPGA-Specific Considerations

Modules 05–09 apply to any DDR4 interface. This module covers what changes when the controller lives inside an FPGA: hardened PHY resources, calibration hardware, and the pin-assignment rules a schematic can't violate.

Hard vs. soft memory controller, revisited

Module 01 introduced this distinction; here's what it actually changes in the design:

Hard (hardened) PHY Soft (fabric-based) PHY
Delay lines & leveling Dedicated silicon per I/O, vendor-characterized Built from fabric primitives, more design/verification effort
Max data rate Generally higher, vendor-guaranteed Lower, depends on fabric timing closure
Flexibility Fixed pin locations for the hardened bank More placement freedom, at a cost
Where it shows up Most mid/high-end FPGAs' dedicated memory banks Smaller or older FPGA families, or non-memory banks
Confirm which type your target FPGA uses before finalizing pin assignment — hard PHYs generally lock you into specific physical pins for CK/DQS/DQ, which then drives your device placement and routing (Module 09), not the other way around.

DCI / OCT: on-chip termination and impedance calibration

Diagram

Both output driver impedance and on-chip termination on the FPGA side are usually calibrated at runtime against one precision external resistor — variously called DCI (Digitally Controlled Impedance), OCT (On-Chip Termination), or similar depending on vendor. This is the FPGA-side equivalent of the DRAM's own ODT (Module 07).

FPGA I/O Bank DCI/OCT calibration engine Rref precision pin Calibrated drive/ termination applied to every DQ/DQS pin
Get the DCI/OCT reference resistor value and pin location wrong (or forget it entirely) and every I/O in that bank calibrates against the wrong target — a bank-wide impedance error rather than a single-net problem.

Pin-swap rules within a byte lane

FPGA vendors publish exactly which pins can be freely reassigned during layout and which are fixed — using this freedom well is what lets the routing in Module 09 actually converge cleanly.

Signal Swappable? Why
DQ bits within one byte lane Usually yes, freely Controller logically remaps bit order — physical order doesn't matter
DQS/DQS# pin location No — fixed per hardened lane Tied directly to the dedicated PHY delay/leveling hardware
Address/command bits Sometimes, within defined groups Vendor-defined groups only — check the pin guide, don't assume
CK/CK# No Fixed hardened clock pin pair per bank
Byte lane to byte lane Rarely, or only in specific device families Each lane usually maps to one fixed hardened PHY slice
Use the vendor's pin-planner tool rather than hand-assigning — it enforces these swap rules automatically and flags illegal reassignments before you commit to a footprint.

I/O bank voltage grouping & VREF placement

  • Every pin in an I/O bank shares one voltage standard — an entire bank must be dedicated to the DDR4 I/O standard (e.g., SSTL-135/POD12), not mixed with unrelated 3.3V I/O.
  • VREF is normally supplied on dedicated pins within the bank, not synthesized locally — plan for those pins from the start of pin assignment.
  • Confirm how many DDR4 byte lanes a single bank can host before you commit to a device — running out of hardened lanes mid-design forces a device change late.

Where read/write leveling actually happens

The CK-to-DQS skew that Module 09 flagged as uncorrectable by routing alone is exactly what write leveling exists to fix — and it runs in the FPGA's hardened PHY (or soft equivalent), not in the DRAM. At power-up, the memory-interface IP sequences through write leveling, read (DQS gating and centering) leveling, and periodic recalibration, entirely automatically once configured correctly.

This is precisely why Module 11's bring-up checklist treats a "calibration failure" log message as a pointer back to Modules 04/06/07/09 — the FPGA's leveling engine is reporting that the physical interface it's compensating for is out of its correction range.

Use the vendor memory-interface IP wizard

Every major FPGA vendor ships a memory-interface generator (part of the IP catalog/IP integrator flow) that takes your DRAM part, speed grade, and topology as input and produces the controller, PHY configuration, and a pin-assignment report. Treat its output pin report as a cross-check against Module 09's routing plan — not as a replacement for understanding why the rules exist.

Key takeaways

  • Hard PHYs give higher guaranteed data rates but lock CK/DQS/CA to fixed physical pins — confirm this before finalizing placement.
  • DCI/OCT calibrates the FPGA's own drive and termination impedance against one precision reference resistor per bank.
  • Pin-swap freedom exists mainly within a byte lane's DQ bits — DQS and CK are normally fixed; use the vendor pin planner rather than hand-assigning.
  • Each I/O bank is one voltage standard, with dedicated VREF pins — plan bank/lane budget before committing to a device.
  • Write/read leveling runs inside the FPGA's PHY specifically to correct CK-to-DQS skew — a calibration failure is a signal to revisit Modules 04, 06, 07, and 09.
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