Module 02 Checklist

Component Selection & Reading Datasheets

Before a single trace gets routed, two decisions lock in most of your design constraints: which memory device, and which FPGA family/speed grade. Get these right by actually reading the datasheets — here's how.

DDR technology decision matrix

Beyond the speed/voltage numbers from Module 01, weigh these four practical factors before locking in a memory family:

Factor DDR3 DDR4 DDR5 LPDDR4/5
Cost Lowest (mature, high volume) Moderate Highest (newest) Moderate–high (packaging cost)
Density available Up to 8 Gb typical Up to 16 Gb per die, more with stacking Higher per-die density Package-on-package, moderate density
EOL / availability risk Rising — being phased out Low — mainstream today Low risk but limited second sources yet Low, but fewer vendors than standard DDR
Design effort Well-understood, many reference designs Well-supported by FPGA tool flows Newer tool flows, less community reference Simplified topology, but tight package routing
Default recommendation: unless you have a specific reason (extreme low power → LPDDR, cutting-edge bandwidth → DDR5, legacy BOM → DDR3), DDR4 remains the safest first choice — best combination of tool support, reference designs and component availability.

Step 1: Confirm FPGA memory-controller compatibility

Before choosing a specific DRAM part, confirm your FPGA family actually supports it. In the FPGA vendor's memory-interface datasheet/user guide, look for:

  • Supported memory standards — which of DDR3/4/5/LPDDR4/5 this family's hard controller (if any) supports.
  • Max supported data rate per speed grade — a "-1" (slowest) grade might cap out well below the DRAM's rated speed.
  • Number of memory interfaces available and which I/O banks they're restricted to (Module 10).
  • Hard vs. soft controller availability for your chosen standard — not every family has a hard controller for every standard.
⚠ A common first-project mistake: picking a DDR4-3200 DRAM, then discovering the chosen FPGA's hard controller (or the affordable speed grade) tops out at 2400 MT/s. Check the FPGA side first — it constrains everything downstream.

Step 2: Reading a DRAM datasheet

Every DRAM datasheet follows a similar shape. Here's a typical DDR4 part number decoded (values are illustrative — always confirm against the specific manufacturer's decoder table):

MT40A512M16LSA-062E
MT40A — manufacturer + DDR4 family prefix
512M — density per I/O (512M × organization)
16 — organization: x16 (also seen: x4, x8)
LSA — package/die revision code
-062E — speed grade (e.g., 062 ≈ DDR4-3200, CL22)

Once you've decoded the part number, the rest of the datasheet has four sections you'll return to constantly:

Section What to look for Used in
Timing parameter table tCK, CL, tRCD, tRP, tRAS, tRC, tRFC, tFAW, tWTR, tRRD, tCCD Module 03
Electrical characteristics (DC/AC) VDD, VDDQ, VPP, VREF, VIH/VIL, ODT resistance options Modules 03, 07, 08
IDD current tables Per-operation current draw — sizes your power rails Module 08
Package & ball map Physical pinout, ball pitch, thermal pad if present Module 09

Step 3: Reading the FPGA memory-interface guide

The FPGA vendor's memory-interface (e.g. MIG/EMIF-class) documentation has its own must-read sections:

  • On-chip termination / DCI / OCT options — what impedances the I/O can present without a discrete resistor (feeds Module 07).
  • Calibration requirements — what the controller needs at power-up to perform read/write leveling (feeds Modules 04, 10).
  • Pin-swap rules — which pins within a byte lane or bank can be freely reassigned during layout without breaking function, and which are fixed (dedicated clock/config pins). Critical input for Module 09's routing.
  • I/O bank voltage & grouping rules — which bank(s) must be dedicated to the memory interface and at what voltage (Module 10).
Treat the FPGA memory-interface guide as equally important as the DRAM datasheet — most real-world bring-up issues trace back to a pin-swap or termination rule that was in this document and got missed.

Component-selection checklist

Interactive

Reusable per project — check items off as you confirm them.

  • FPGA family/speed grade supports the target DDR standard and data rate
  • Hard controller available for this standard, or soft-controller resource budget confirmed
  • DRAM density and organization (x8/x16) match required bus width and ECC needs
  • DRAM speed grade (CL, tCK) is at or above the interface's target rate
  • On-die termination options in both DRAM and FPGA datasheets reviewed (Module 07)
  • Pin-swap rules and dedicated pins identified in the FPGA memory-interface guide
  • Package/ball map obtained for both devices (needed for Module 09 breakout planning)
  • Second-source / EOL risk checked for the specific part number

Key takeaways

  • Confirm FPGA memory-controller compatibility before selecting a specific DRAM part — the FPGA side constrains everything else.
  • A DRAM part number encodes density, organization, package and speed grade — always decode it against the manufacturer's own table.
  • Four datasheet sections matter most: timing table, electrical characteristics, IDD current tables, and the package/ball map.
  • The FPGA memory-interface guide's termination, calibration and pin-swap rules are just as important as the DRAM datasheet.
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