Module 11
Checklist
Design Checklist, Common Mistakes & Bring-Up
Before fabrication: one consolidated checklist across every module. After fabrication: what to look at first when the board powers up, and how to map a bring-up symptom back to the module that explains it.
Pre-fabrication master checklist
Component & datasheet (Module 02)
- DRAM speed grade confirmed compatible with FPGA memory-controller Fmax
- Timing table, IDD current tables, and package/ball map all reviewed, not just the summary page
Topology (Module 04)
- Fly-by used for all CA/CK/control nets (never T-branch) on discrete DDR4
- Devices-per-byte-lane fan-out within the FPGA's supported limit
Signal integrity & termination (Modules 06–07)
- Via stubs on critical nets minimized or back-drilled
- VTT termination present at the true end of the CA fly-by bus
- ODT modes (RTT_NOM/WR/PARK) selected to match topology and loading
Decoupling & PDN (Module 08)
- Decoupling stack covers DC through several hundred MHz with no impedance gap over target
- High-frequency MLCCs placed with shortest possible loop to each power ball
Layout & routing (Module 09)
- All length-matching tolerances verified against the vendor's routing guide, not general rules of thumb
- Continuous reference plane under every DDR signal layer
- Fly-by device order preserved consistently across every CA/CK/control net
FPGA-specific (Module 10)
- DCI/OCT reference resistor present at the correct value and pin
- Pin assignment cross-checked against the vendor memory-interface IP wizard's report
- I/O bank fully dedicated to the DDR4 voltage standard, VREF pins accounted for
The most common mistakes, ranked by how often they bite
| # | Mistake | Symptom | Module |
|---|---|---|---|
| 1 | T-branch/star routing of CA/CK on discrete DDR4 | Interface never trains at power-up | 04 |
| 2 | Missing or misplaced VTT termination on the fly-by bus | Never trains, or trains intermittently | 07 |
| 3 | Reordered fly-by device sequence on one net | One bit consistently fails at higher speed grades only | 04 / 09 |
| 4 | Insufficient high-frequency decoupling near power balls | Random, data-pattern-dependent bit errors | 08 |
| 5 | Byte lane length matching out of tolerance | Marginal read/write margins, fails only at high speed grade or temperature extremes | 09 |
| 6 | Wrong or missing DCI/OCT reference resistor | Whole bank shows impedance-related SI issues | 10 |
| 7 | VREF trace routed too close to a switching aggressor | Elevated bit-error rate, worse under sustained traffic | 05 / 06 |
| 8 | Speed grade mismatch between FPGA controller and DRAM part | Interface trains but throughput/Fmax falls short of spec | 02 |
Bring-up sequence
1. Power rails up, sequencing correct
→
2. RESET# release, CKE/clock stable
→
3. Mode register init (CL, RTT, DCI)
→
4. Write leveling
→
5. Read (DQS gating/centering) leveling
→
6. Calibration pass / traffic test
Most memory-interface IP reports calibration status per stage (often over JTAG/UART or a status LED/register). Knowing which stage failed narrows the search dramatically — a failure at stage 1–2 is almost always power/reset sequencing; a failure at stage 4–5 almost always points back to Modules 04, 06, 07, or 09.
Symptom → likely cause → module to revisit
| Symptom | Likely cause | Revisit |
|---|---|---|
| Board never leaves reset / no calibration attempt | Power sequencing, reset timing, or clock not stable | Module 08 (PDN), datasheet power-up sequence |
| Calibration fails every time, same stage | Structural SI/termination/topology issue | Modules 04, 06, 07, 09 |
| Calibration passes, but fails intermittently under load | Marginal SI or PDN margin, temperature/voltage sensitive | Modules 06, 08 |
| Works fine at low speed grade, fails at rated speed | Length matching, termination, or decoupling margin too tight for the timing budget | Modules 07, 08, 09 |
| One specific bit/lane always fails | That lane's routing, termination, or pin assignment | Modules 05, 09, 10 |
Bring-up debugging is almost always a matter of mapping a symptom back to one of
Modules 04–10 rather than a brand-new problem — the checklist above exists so you
rarely need this table at all.
Key takeaways
- A pre-fabrication checklist that spans every module catches the overwhelming majority of "board never trains" failures before they happen.
- Topology and termination mistakes (T-branch routing, missing VTT) are the single most common root cause of total calibration failure.
- Bring-up failures map cleanly back to a small set of modules — use the calibration stage that failed to narrow the search immediately.
- "Works at low speed, fails at rated speed" almost always means a margin problem, not a broken connection — revisit termination, decoupling, and routing tolerances together.