Module 04 Animated

Memory Topologies

How command, address, clock and data physically connect the FPGA to one or more DRAM devices shapes almost every decision downstream — termination, length matching, and even how many devices you can use at all.

Ranks, and discrete vs. module

  • Single-rank — one set of DRAM devices responds to each chip-select; simplest, lowest capacitive load.
  • Dual-rank — two sets share the data/address bus but respond to separate chip-selects, doubling capacity at the cost of extra bus loading.
  • Discrete (soldered-down) devices — the norm for FPGA designs: DRAM ICs placed directly on the board, giving full control over topology and length matching.
  • DIMM/SODIMM sockets — modular and field-upgradeable, but the module's internal topology is fixed by the module vendor; less common in embedded FPGA designs.
This course assumes discrete devices throughout — the far more common choice for FPGA board designs, and the case where topology is entirely in your hands.

Fly-by vs. T-branch vs. point-to-point

Animated

Watch the pulse travel in each topology below — notice when it reaches each device.

Fly-by (DDR3/4/5 command/address/clock)

FPGA D0 D1 D2 D0 sees it first, D2 last — leveling compensates

T-branch / star

FPGA D0 D1 D2

All devices see it together — but the junction itself causes reflections at DDR4 speeds

Point-to-point (LPDDR4/5)

FPGA LPDDR

Single short, direct link — simplest topology, minimal termination needed

Why DDR3/DDR4/DDR5 mandate fly-by

A T-branch junction is electrically a discontinuity: at DDR4 speeds the trace impedance seen at the split doesn't match a single trace's impedance, causing reflections back toward the source. Fly-by avoids the junction entirely — CA/CK is a single continuous trace that simply passes each device in turn.

The trade-off: devices further down the fly-by chain see every command later than devices near the source. Rather than fight this with layout alone, the controller's read/write leveling (Module 03) measures and compensates for it per device — which is precisely why DDR3 and later require fly-by topology and a leveling-capable controller.

⚠ T-branch/star CA/CK topology is a legacy pattern from slower memory generations. Using it on a DDR4 design (even "because it seemed simpler to route") is one of the most common root causes of a board that never trains/calibrates at power-up.

Why LPDDR4/5 gets to skip all this

LPDDR4/5 is designed for point-to-point connections — typically one FPGA/SoC to one (or a small number of) package-on-package or nearby discrete devices, with very short traces. There's no fly-by chain to level, and often no external termination network at all (Module 07) — a direct consequence of the topology being this simple.

Devices per byte lane & fan-out limits

Consideration Guidance
Data (DQ/DQS) fan-out Point-to-point per byte lane — one device's DQ/DQS group does not fan out to another device.
CA/CK fan-out Shared fly-by bus — every device on the same chip-select group taps the same CA/CK trace.
Loading vs. trace length More devices on the fly-by chain increases total trace length and capacitive loading — check the controller's max fly-by length spec.
Typical practical limit Most FPGA designs use 1–2 devices per byte lane's worth of CA/CK fan-out before signal margin becomes the limiting factor (Module 06).

Key takeaways

  • Discrete devices (not DIMM sockets) are the norm for FPGA designs — you control the topology.
  • Fly-by avoids the impedance discontinuity of a T-branch junction; the resulting per-device delay is corrected by read/write leveling, not layout alone.
  • Point-to-point topology (LPDDR4/5) sidesteps the whole problem — no chain, minimal termination.
  • Data (DQ/DQS) is point-to-point per device; only CA/CK is shared across a fly-by chain.
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