Bonus Real Parts Diagrams

Worked Example: Versal SoC + Dual x16 DDR4

A concrete pairing of a real AMD Versal adaptive SoC and two real 16-bit-wide DDR4 devices wired in parallel for a 32-bit interface — with every design decision traced to a specific parameter in one or both datasheets.

The scenario

Two identical 16-bit-wide (x16) DDR4 components are placed side by side and wired to share one command/address/clock bus, while each keeps its own data byte lanes — exactly the "devices per byte lane" pattern from Module 04, applied to build a 32-bit-wide, single-rank, component-based (non-DIMM) DDR4 interface for a Versal SoC memory controller.

32-bit
Total data width (2 × x16)
2 GB
Total capacity (2 × 8Gb)
DDR4-3200
Speed grade, CL22
1 rank
Single-rank, component architecture

The bill of materials: two real parts

FPGA / SoC — AMD Versal AI Core series

XCVC1902-2MSEVSVA2197

Versal adaptive SoC with a hardened DDR Memory Controller (DDRMC) attached to the on-chip Network-on-Chip (NoC) — DDR4/LPDDR4/LPDDR4X are supported directly in hardened silicon rather than built from FPGA fabric, which is the Versal-specific angle Module 10 introduced.

Reference docs: DS950 — Versal Architecture and Product Data Sheet: Overview (device/NoC architecture); AM011 — Versal ACAP Technical Reference Manual, "DDR4 Memory Controller" chapter (DDRMC capabilities, PHY calibration); AM013 — Versal ACAP Packaging and Pinouts Architecture Manual (bank diagrams for the VSVA2197 package); PG313 — Versal Adaptive SoC Programmable NoC and Integrated Memory Controller Product Guide, "Pinout Rules" chapter (which banks/pins the DDRMC can legally use); UG863 — Versal Adaptive SoC PCB Design User Guide (DDR4 signal/termination/routing rules, used throughout this page).

DDR4 SDRAM — Micron, x16, DDR4-3200

MT40A512M16LY-062E:E

8Gb (512 Meg × 16) DDR4 SDRAM, 96-ball FBGA, 1.2V VDD/VDDQ, DDR4-3200 CL22 speed bin. Two of these devices, identical part number, are placed in parallel — the exact requirement Module 04/07 flagged for a clean fly-by bus.

Reference doc: Micron "8Gb: x4, x8, x16 DDR4 SDRAM" datasheet (MT40A512M16 family) — Features/Ballout, Electrical Characteristics, ZQ Calibration, Mode Register 1 (MR1), and AC Timing/Speed Bin Table sections are cited by name throughout this page.
Straight from UG863: "When creating a DDR4 interface, all components in the interface must share the same part number, data width, density, and speed grade." Both DDR4 devices here must be the exact same orderable part number — not just the same density or speed bin.

Block diagram

Diagram
Versal SoC XCVC1902 Hard DDRMC (bank 700/701) CA / CK / CTRL — shared fly-by bus 39Ω VTT DDR4 x16 #1 MT40A512M16 DQ[15:0] DDR4 x16 #2 MT40A512M16 DQ[31:16] DQ[15:0]/DQS[1:0]/DM[1:0] — point-to-point to #1 DQ[31:16]/DQS[3:2]/DM[3:2] — point-to-point to #2 ZQ 240Ω ZQ 240Ω IO_VR 240Ω → VCCO Two identical MT40A512M16 devices, one shared CA/CK/CTRL bus, two independent data byte-lane groups

Parameter cross-reference: what drives each circuit decision

This is the table that actually connects the two datasheets — every value below comes from a named section or field in one datasheet, cross-checked against the other.

Design decision Versal-side reference Micron-side reference Resulting circuit value
CA/CK/CTRL termination UG863, "Signals and Connections for DDR4 Interfaces": address/command/control signals require 39 Ω to VTT at the far end, fly-by routing Datasheet input pin electrical spec confirms standard fly-by-compatible input receivers on address/command pins 39 Ω ± resistors from the last device's CA/CK/CTRL pins to a VTT rail
Differential clock impedance UG863, "Physical Design Rules for DDR4 Signals": differential CK/DQS impedance 90 Ω ± 10% CK_t/CK_c differential input characteristics (AC/DC input spec, Clock section) Route CK_t/CK_c as a 90 Ω differential pair, tightly coupled
Single-ended CAC/data impedance UG863, "Physical Design Rules for DDR4 Signals": single-ended CAC and data signal impedance 50 Ω ± 10% Single-ended input/output characteristics (SSTL/POD-class I/O spec) Target 50 Ω single-ended trace impedance for CA and DQ
DQ/DQS/DM termination UG863 signal table: data and strobe signals use no PCB termination — ODT only, point-to-point routing Mode Register 1 (MR1): RTT_NOM field (bits 9, 6, 2) selects the on-die termination value the device applies internally No board resistors on DQ/DQS/DM; select RTT_NOM via mode-register init in the memory IP
FPGA-side I/O calibration UG863 signal table: IO_VR_7xx/8xx calibration reference, 240 Ω to VCCO_7xx/8xx; AM011 DDRMC PHY calibration description — One 240 Ω ± 1% resistor from the IO_VR pin to VCCO on each I/O bank used by the DDRMC
DRAM-side ZQ calibration — ZQ Calibration section: 240 Ω ± 1% reference resistor from ZQ pin to GND, used to calibrate Ron/RTT over PVT One 240 Ω ± 1% resistor per device, ZQ pin to GND
Speed grade / timing budget AM011, "DDR4 Memory Controller" chapter: maximum supported data rate for the selected DDRMC configuration AC Timing/Speed Bin Table: DDR4-3200 CL22 → tCK = 0.625 ns, tRCD = tRP = 22 × tCK = 13.75 ns Confirm the DDRMC configuration in the memory IP is set for 3200 MT/s, CL22 before layout
Supply voltage UG863, "Versal Adaptive SoC Power Rails": VCCO for the DDR4 bank set to the POD12 1.2 V I/O standard Electrical Characteristics: VDD = VDDQ = 1.2 V ± 60 mV (1.14–1.26 V) Shared 1.2 V rail feeds both the DDRMC bank VCCO and both DRAM VDD/VDDQ pins
RESET_N UG863 signal table: RESET_N — 4.7 kΩ to GND at far end, fly-by RESET_n pin description: power-up/reset sequencing input, held low during initialization One 4.7 kΩ pulldown, fly-by net from the Versal reset output to both devices
Trace length / via budget UG863, "Physical Design Rules for DDR4 Signals": max 11,000 mils (CAC), 5,500 mils (data/strobe); via count ≤ (2 × device count) + 2 for CAC — For 2 devices: CAC via budget ≤ 6; keep both DDR4 packages within the length envelope
Package/ballout cross-check Versal package pin table for the selected I/O bank (per XCVC1902 package files) Ballout diagram: 96-ball FBGA, DQ/DQS/DM grouping per byte Verify byte-lane pin assignment against Micron's ball map before locking the footprint (Module 09/10)

Which FPGA pins to use — and why

Diagrams

This is the one place Versal design genuinely differs from a soft-controller FPGA: you do not hand-pick individual balls for CK/CA/DQ. Module 10 established that the hard DDRMC has a fixed physical PHY; here's what "pin selection" actually means in practice, and why each step is done the way it is.

Straight from the Versal ACAP Technical Reference Manual (AM011): "I/Os in some banks on the left and right edges of the XPIO rows do not have direct access to all I/O logic resources and can only be used for DDR memory controller (DDRMC)" applications. Those banks are not general-purpose — they exist specifically to reach the hardened DDRMC.
Step What you actually choose Reason
1. Pick a DDRMC-capable bank, not any XPIO bank Only the specific XPIO banks wired to a DDRMC slice on the die can host a DDR4 interface AM011 confirms these edge banks "can only be used for DDR memory controller (DDRMC)" — a generic XPIO/HDIO bank has no DDRMC datapath behind it at all, so it is physically not an option, not just a poor choice
2. Check that bank's I/O budget against the byte-lane count needed Confirm the chosen DDRMC-capable bank(s) on the XCVC1902/VSVA2197 combination (per AM013's "VC1902 Bank Diagram Overview" for that package) provide enough sites for 4 byte lanes (32-bit) plus the shared CA/CK/CTRL group Each XPIO bank provides a fixed number of XPHY sites (9 per bank, up to 54 single-ended I/O per UG1273); running out mid-design forces a bank or device change, so this is checked before layout, not after
3. Keep both DDR4 devices on the same DDRMC instance Both MT40A512M16 devices' byte lanes must land in the same memory-controller instance / adjacent banks, never split across two independent DDRMCs A single DDRMC schedules one logical rank; splitting one rank's byte lanes across two controllers isn't a supported topology — this is the FPGA-side twin of Module 04's "one shared command/address domain" rule
4. Let the Vivado NoC/DDRMC IP wizard assign the physical pins Specify the DRAM part (MT40A512M16), width (32-bit), rank count (1), and component (not DIMM) architecture in the AXI NoC / DDRMC IP customization GUI; the wizard emits the CK/CA/CTRL/DQS pin-to-ball mapping PG313's "Pinout Rules" chapter defines a fixed silicon-level mapping between each bank's balls and the DDRMC's internal byte lanes — this mapping is enforced by the tool, not editable by hand, echoing Module 10's "DQS and CK pins are fixed" rule
5. Use only the DQ-within-byte-lane swap table the wizard reports The single remaining degree of freedom is reassigning which physical DQ ball carries which data bit inside one byte lane Matches Module 10's pin-swap rules exactly — DQ bits swap freely, DQS/CK do not
6. Cross-check the exported XDC before schematic capture Compare the wizard's generated constraints against PG313's Pinout Rules chapter and AM013's bank diagram for the VSVA2197 package AMD's own XTP546 "Versal Adaptive SoC Schematic Review Checklist" exists specifically to catch illegal or suboptimal DDR pin assignments before tape-out — this is the formal gate before Module 09's routing begins
In short: for a hard-DDRMC device like Versal, "selecting pins" means selecting the right bank and letting the memory IP wizard lock the CK/CA/CTRL/DQS mapping for you — the designer's real decisions are which DDRMC-capable bank to dedicate to this interface and confirming it has enough I/O for a 32-bit, 2-device fly-by bus.

Capacity and width, worked out

  • Each MT40A512M16 is 512 Meg × 16 = 8 Gb of capacity, in a single x16 device.
  • Two devices in parallel double the data width (16 → 32 bits) while the shared CA/CK/CTRL bus keeps both devices addressed together — this yields 8 Gb + 8 Gb = 16 Gb = 2 GB total, at 32 bits wide.
  • Each device contributes one independent data byte-pair group (DQ[15:0]/DQS[1:0]/DM[1:0] and DQ[31:16]/DQS[3:2]/DM[3:2]) — the same "devices per byte lane" pattern from Module 04/05, just with x16 devices instead of x8.

Key takeaways

  • Every termination and impedance value in this design traces to a named table in UG863 (Versal PCB Design User Guide) — nothing here is a rule of thumb.
  • ODT/RTT_NOM lives entirely in the Micron datasheet's Mode Register 1 field; the board carries no DQ/DQS termination resistors at all.
  • ZQ (DRAM-side) and IO_VR (Versal-side) are the same idea on opposite ends of the interface — a precision 240 Ω reference resistor that calibrates on-die impedance over PVT.
  • Both DDR4 devices must be the exact same part number, per UG863's explicit requirement — this isn't optional for a component-based fly-by bus.
  • Capacity and width scale independently: adding a second x16 device doubles width (16→32 bit), not depth — depth would require a second rank instead.
  • "Selecting FPGA pins" on Versal means selecting a DDRMC-capable bank and letting the memory IP wizard lock the CK/CA/CTRL/DQS mapping (per PG313's Pinout Rules) — not hand-picking individual balls.

References

Every value and rule cited on this page traces to one of the documents below.

AMD / Versal

Micron / DDR4 device

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