References, Checklist & FAQ
Where to look things up, the 15 checks that catch nearly every FPGA power escape, and the questions every reviewer asks.
References worth bookmarking
- Your FPGA family's datasheet — DC & switching characteristics: rail specs, tolerances, sequencing, ramp windows.
- Vendor PCB/power design guides (AMD UG483/UG583-class, Intel power delivery guides, Lattice/Microchip board design guides) — decoupling tables, consolidation rules, layout examples.
- Power estimators: AMD XPE, Intel EPE — rerun whenever the design's utilization changes materially.
- Regulator-vendor FPGA power pages (TI, ADI, Infineon, Renesas, MPS) — reference designs mapped to specific FPGA families.
- Deeper on this platform: SI Academy — Power Integrity, Conducted Emissions, Heat Sink design.
The 15-point FPGA power review checklist
Ticks are visual only. Print for design reviews.
FAQ
How many power rails does an FPGA need?
Between 3 (small Lattice/iCE parts: core, I/O, aux) and 9+ (transceiver-heavy devices). Count comes from the datasheet's supply table after merging what the vendor's consolidation rules allow — typically you end up with 4–6 regulators.
Can VCCINT and VCCBRAM share a regulator?
Usually yes when they're specified at the same voltage — the vendor's consolidation table is the authority. VCCINT and transceiver AVCC must not share, even at identical voltages: core switching noise destroys the jitter budget.
What order should FPGA rails power up?
Typically core → aux → I/O, reverse on the way down, with transceiver rails per their own note — but this is family-specific. Some families also accept "all rails within a window". Implement with a PGOOD chain or sequencer, and verify with a scope capture.
Buck or LDO for transceiver rails?
A low-noise LDO (often fed from an intermediate buck rail) is the default — transceiver rails typically want < 10 mV p-p ripple and low µV-RMS noise. A very quiet buck plus filtering can work at higher currents, but validate against the jitter budget with eye scans.
How much decoupling does an FPGA need?
Start from the vendor's per-rail decoupling table; compute Ztarget = ΔV/ΔI when your transient profile is unusual. It's a mix across decades — bulk, ~µF MLCCs, and 100 nF at the balls — with placement (mounted inductance) mattering as much as the count.
Why won't my FPGA configure after a power change?
The usual suspects: sequence order changed, a ramp became non-monotonic (soft-start vs big output caps), a ramp fell outside the allowed window, or VCCAUX now arrives late. Single-shot capture all rails + INIT_B/DONE and compare against your archived golden sequence.
Course complete 🎉
You can now take any FPGA from datasheet rail table to a sequenced, decoupled, thermally sane, scope-verified power design. Continue with the Signal Integrity Academy for deep PDN theory, or the I2C Academy — your PMBus/sequencer management bus runs on it.