Module 06 Calculator

Layout & Thermal

A perfect schematic dies in a bad floorplan: sense lines through switch nodes, amps squeezed through two vias, LDOs cooking at 150 °C. The rules here are cheap on day one and impossible on day ninety.

Floorplan & placement

  • PoL bucks close to the FPGA — VCCINT's regulator within a few cm; resistance of a long 1.0 V path eats the tolerance stack (1 mΩ at 10 A = 10 mV!).
  • Keep switch nodes tiny and contained: the SW copper is the EMI antenna — minimal area, no routing under it, input cap loop as tight as physically possible.
  • Switchers away from MGT rails/lines: place low-noise LDOs and transceiver supplies on the quiet side of the board; never route a switch node near transceiver pairs.
  • Orient bucks so their input loops share the input bulk caps naturally; star the input from the connector's bulk capacitance.

Planes, vias & current density

  • A plane (or fat pour) per major rail, tightly coupled to ground — this is both the low-inductance PDN interconnect (Module 05) and the DC path.
  • Via math: a 0.3 mm via is good for roughly 1–2 A continuous; a 10 A VCCINT path wants 8–12 stitching vias at every layer change. Spread them; don't share one via between the cap and the load.
  • Check copper weight: 1 oz outer/inner is marginal above ~6 A on narrow pours — go 2 oz or widen.
  • Thermal relief kills power vias' effectiveness — use solid connections on power nets (talk to your fab about assembly needs).

Remote sense: route it like a signal

Buck 1.0 V FB / GNDS pins FPGA VCCINT ball field high-current path (plane, many vias) Kelvin sense pair — quiet route, no current

Sense at the load, not the inductor. Route the pair together, away from switch nodes, with an RC filter per the regulator datasheet.

LDO thermal quick-check

Calculator
Dissipation P = (Vin−Vout)·I —
Temperature rise —
Junction temperature —
Efficiency —
θJA on the datasheet assumes the JEDEC test board — your real number depends on copper area. More pour + more thermal vias = lower θJA. If TJ is marginal, drop Vin (better intermediate rail) before adding copper. Deep dive: the Heat Sink training.

Key takeaways

  • Place VCCINT's buck close; every milliohm of path is millivolts of your budget.
  • Planes per rail, solid via farms at layer changes, real copper weight for amps.
  • Remote sense is a quiet Kelvin pair to the ball field — treat it as a signal.
  • Run the (Vin−Vout)·I·θJA check on every LDO before layout, not after.
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