Module 04 Animated

Power Sequencing

Rails up in the wrong order and the FPGA may draw excess current, fail to configure, or slowly damage itself through parasitic paths. The fix costs a PGOOD wire — if you design it in.

Why order matters

  • Parasitic/latch-up paths: I/O rails up before the core can forward-bias internal structures — excess current, long-term damage.
  • Configuration reliability: the config engine needs VCCINT + VCCAUX stable before it starts; violate the ramp window and the FPGA may not load its bitstream.
  • Bus contention: unconfigured I/O drifting while a live 3.3 V bank drives into it stresses both chips.
  • Datasheet law: every family specifies a recommended order, ramp-rate window (e.g. 0.2–50 ms), and monotonic ramp requirement. These are requirements, not suggestions.
Typical required order — up: VCCINT → VCCBRAM → VCCAUX → VCCO (MGT rails per their own note, usually after AUX). Down: exact reverse. Always confirm in your family's datasheet DC/switching chapter.

The PGOOD chain in action

Animated
VCCINT VCCAUX VCCO RESET_n PGOOD₁ → EN₂ PGOOD₂ → EN₃ supervisor delay done → FPGA configures ✓ each rail's PGOOD enables the next; the supervisor holds reset until all rails are valid

PGOOD daisy-chain: order is guaranteed by wiring, not firmware. Note every ramp is monotonic — no dips, no plateaus below threshold.

Three implementation patterns

Pattern Order control Down-sequence? Fault handling Fits
PGOOD chain Hard-wired No (falls as it falls) Rail failure stops the chain ≤ 4–5 rails, most boards
PMIC sequencer Programmed slots + delays Yes, reverse slots Configurable retry/latch-off PMIC-based trees
Sequencer / PMBus manager IC Fully programmable Yes, monitored Fault logging, telemetry, margining 6+ rails, servers, hot-swap
Down-sequencing is the forgotten half. A wall-wart yank removes the input while bulk caps discharge at their own rates — check whether your family requires controlled power-down (many are tolerant, some MGT rails are not). If required, use a sequencer with down-slots and enough input hold-up.

Ramp rules

  • Monotonic: no dips on the way up — a non-monotonic VCCINT ramp can corrupt configuration. Watch for soft-start interacting with large output capacitance.
  • Ramp window: too fast (< ~200 µs) can trip inrush/latch-up limits; too slow (> ~50 ms) can hang POR circuits. Set buck soft-start inside the window.
  • Pre-bias safe: regulators must not sink current from a rail partially charged through parasitic paths — use pre-bias-safe bucks (most modern sync bucks are; verify).
  • Simultaneity option: some families allow "all rails together within X ms" as an alternative to strict ordering — sometimes simpler with one PMIC. Read the fine print.

Key takeaways

  • Sequence order, ramp window, monotonicity: all three are datasheet requirements.
  • PGOOD chaining gives hardware-guaranteed order for the price of a few traces.
  • Verify EN thresholds and PGOOD pull-up rails — the classic chain bugs.
  • Plan power-down too, and always capture the real sequence on a scope (Module 07).
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