Module 02 Plotly

How to Select Components

Architecture first, then parts: bucks for amps, LDOs for quiet, inductors that don't saturate, and capacitors that are still capacitors at their working voltage.

Step 1 — Choose the architecture

Approach Best for Pros Cons
Discrete regulators (one buck/LDO per rail) 2–4 rails, cost-driven, full control Cheapest BOM, per-rail optimization Most design + layout effort; DIY sequencing
Multi-rail PMIC 4–8 rails, space-constrained Built-in sequencing, one datasheet, small area Rail current limits; single-vendor lock
FPGA-ready power module Fast time-to-market, high current Pre-validated against vendor rail specs, integrated magnetics Cost; limited flexibility
Vendors publish reference power designs per FPGA family (TI, ADI, Infineon, Renesas all maintain FPGA power pages). Start from one — the rail grouping and sequencing homework is already done, then swap parts as needed.

Selecting bucks (the amps)

  • Output current: margined rail current (Module 01) with headroom at max ambient — check the derating curve, not the headline number.
  • Transient response: for VCCINT, prefer fast control loops (constant-on-time/D-CAP class) — they recover from load steps in µs and need less output capacitance to meet the droop budget.
  • Switching frequency: 500 kHz–2 MHz typical; higher f = smaller L/C but more switching loss, and keep it away from sensitive bands (plan vs your EMC needs).
  • Integrated vs external FETs: integrated to ~15–20 A; controllers + external FETs (or multi-phase) beyond. Multi-phase also cuts input/output ripple for big VCCINT.
  • Remote sense: non-negotiable on high-current core rails — sense at the FPGA balls, not at the inductor.
  • Soft-start & enable: programmable soft-start and an EN pin are what make Module 04's sequencing possible; verify monotonic ramp.

Selecting LDOs (the quiet ones)

Transceiver rails (VMGTAVCC/AVTT), PLL and ADC supplies want an LDO — or a buck followed by an LDO ("buck-then-LDO") when the current is too high to burn from the input rail directly.

  • PSRR vs frequency: the datasheet's "70 dB PSRR" is at 1 kHz. At the buck's 1 MHz switching frequency it may be 15–25 dB — check the curve at your upstream ripple frequency, and add an LC/ferrite post-filter if it's thin.
  • Output noise: transceiver rails typically want < 100 µVRMS-class LDOs; check the jitter/noise budget in the FPGA's transceiver guide.
  • Dropout & thermal: P = (Vin − Vout) × I. Feeding a 0.9 V/2 A rail from 1.8 V burns 1.8 W — pick the intermediate rail to keep dropout small (e.g. 1.2 V → 0.9 V), and run the junction-temperature check in Module 06.
  • Stability: confirm the LDO is stable with your ceramic-only output network (ESR range).

Inductors: the 30–40 % ripple rule

Size L so peak-to-peak ripple current ΔIL ≈ 30–40 % of rated output: L = Vout·(1 − Vout/Vin) / (fsw·ΔIL). Then check two ratings that are not the same number:

  • Saturation current Isat > Iout + ΔIL/2 — with margin; a saturating inductor's current spikes destroy FETs.
  • Thermal current Irms > Iout — governed by DCR heating; lower DCR = better efficiency at heavy load.

Capacitors: the DC-bias trap

Plotly

Class-II ceramics (X5R/X7R) lose capacitance under DC bias — dramatically in small packages. The "22 µF" 0402 on your 1.8 V rail may really be 8 µF. Every output-capacitance and PDN calculation must use the derated value from the manufacturer's bias curve.

Typical effective capacitance vs DC bias for a 22 µF X5R in three package sizes (representative curves). Bigger package = more ceramic = less derating.

  • Mix types: bulk (polymer/tantalum, stable C, some ESR for damping) + MLCC mid/high-frequency (Module 05 does the math).
  • Input caps see high RMS ripple current — check their ripple rating, place them tight to the buck's VIN/GND loop.
  • Prefer 0603/0805 over 0402 for bulk-ish MLCC duties on low-voltage rails; the derating chart is why.

Sequencing & supervision parts

Option How Use when
PGOOD daisy-chain Rail N's PGOOD drives rail N+1's EN 2–4 rails, simple fixed order
PMIC internal sequencer Order + delays configured by OTP/I2C You chose a PMIC anyway
Dedicated sequencer / PMBus manager Programmable slots, monitoring, fault response, telemetry 6+ rails, compliance/telemetry needs, hot-swap systems
Voltage supervisor Releases FPGA resets only when all rails valid Always — belt and braces for configuration

Worked example: Zynq-7020-class parts table

Representative selection for a 5-rail tree from a 12 V input (parts illustrate the class of device — always re-verify against your current budget):

Rail V / I (margined) Regulator class Example part class Why
VCCINT (+VCCBRAM) 1.0 V / 4 A Sync buck, fast COT loop, remote sense TPS543x / TPS62x-class Droop budget, efficiency at amps
VCCAUX + VCCADC 1.8 V / 1 A Sync buck TPS62x / MP2x-class Mid current, up early in sequence
VCCO banks 1.5 V & 3.3 V / 2 A Sync bucks (one per voltage) TPS62x-class ×2 Set by DDR3 (1.5 V) + peripherals (3.3 V)
VMGTAVCC 1.0 V / 0.8 A Buck-then-LDO, low noise TPS7A5x / LP5912-class LDO from 1.8 V Transceiver jitter budget
VMGTAVTT 1.2 V / 0.6 A Low-noise LDO from 1.8 V same class Termination rail, quiet
Sequencing — PGOOD chain + supervisor TPS3808-class supervisor 5 rails, fixed order suffices

Key takeaways

  • Pick the architecture (discrete / PMIC / module) before any part number.
  • Bucks: transient response and remote sense for VCCINT; derated current at temperature.
  • LDOs: PSRR at the switching frequency, not 1 kHz; thermal check every time.
  • Inductors: Isat and Irms are different ratings — check both.
  • Use derated (DC-bias) capacitance everywhere — especially 0402s.
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