Module 09 Worked Example

Powering an AMD Versal™ AI Edge SoC — End to End

Everything from Modules 01–08 applied to a real device: the Versal AI Edge VE2302, powered with real, orderable part numbers from TI's validated PMP23227 reference design — with the specific datasheet parameter you must check called out at every step.

1 The device and its governing documents

Target device: AMD Versal AI Edge VE2302 (XCVE2302) — a low/mid-power AI Edge adaptive SoC with AI Engines, Arm PS cores, PL fabric and GTYP transceivers. Three documents drive the whole power design:

Document What you pull from it
DS958 — Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics Recommended Operating Conditions table — rail voltages & DC tolerances; Power Supply Sequencing section — required up/down order, ramp windows and POR_B conditions; AC ripple limits per rail.
AMD Power Design Manager (PDM) (successor to XPE for Versal; user guide UG1556) Per-rail current estimates for your configuration, and the official rail-consolidation ("Minimum Rails") options that say which supplies may legally share a regulator.
UG1506 — Versal Adaptive SoC Board System Design Methodology Guide Board-level power methodology, decoupling and PCB guidance.
Rule from Module 01, now concrete: run PDM first. The currents below are the PMP23227 example estimation for a VE2302 at ~50 W system power — your AI Engine utilization can move the 0.8 V group current dramatically.

2 Rail map with AMD's "Minimum Rails" consolidation

Versal lists a dozen supplies; PDM's Minimum Rails option (Module 03's "merge rules", done officially) consolidates them into a buildable set. As used in PMP23227:

Group Versal rails consolidated V I (example) Spec to verify in DS958
Core group VCCINT, VCC_SOC, VCC_PMC, VCC_PSFP, VCC_PSLP, VCC_RAM, VCC_IO 0.80 V 39 A peak ±1 % DC tolerance, ±17 mV AC — sets the transient budget (Module 05) and demands remote sense
I/O VCCO banks (example 1.0 V / DDR-dependent) 1.0 V 3 A VCCO range per I/O standard; PMC-domain VCCO up-first rule
Aux group VCCAUX, VCCAUX_PMC, VCCAUX_SMON 1.50 V 1.1 A ±1 % DC, 10 mV p-p AC ripple limit — note Versal's VCCAUX is 1.5 V, not the 1.8 V of older families!
GTYP analog Transceiver AVCC 0.88 V 0.7 A GTYP supply ripple/noise limits — the jitter budget rail
GTYP termination Transceiver AVTT 1.20 V 1.3 A same section
Housekeeping 1.5 V analog (SMON-class, quiet) / 3.3 V utility 1.5 / 3.3 V 50 / 12 mA low-noise requirement → LDO, not buck
The core group at 0.8 V / ±1 % gives a total window of just ±8 mV DC plus a ±17 mV AC allowance — recall the tolerance stack (Module 01). At 39 A that implies a milliohm-class PDN and mandatory remote sense.

3 Part selection — with the datasheet parameter that justifies each

Parts are from TI's validated PMP23227 Versal AI Edge reference design (8–18 V input, ~50 W). For every selection, the right-hand column names the parameter to verify in that part's datasheet.

Function Part number Why this class of part (Module 02) Datasheet parameters to check
Front-end protection LM74910-Q1 Ideal-diode controller + circuit breaker: reverse-polarity, UV/OV, overcurrent for the 12 V input UVLO/OVLO comparator thresholds & hysteresis (set your 8–18 V window via the UV/OV divider equations); gate-drive charge-pump voltage vs your FET's VGS rating
5 V intermediate bus, 12 A LM25148-Q1 42 V sync buck controller — the intermediate-bus pattern from Module 03 (low-VIN PoL bucks can't take 18 V directly) VIN operating range (3.5–42 V); RT pin frequency-set equation (place fsw off your EMC-sensitive bands); SS pin soft-start capacitor equation — this sets the 5 V ramp that everything downstream sees
0.8 V core group, 39 A TPS62876-Q1 × 2 (stacked) 2.7–6 V input, 25 A stackable synchronous buck — two phases share the 39 A with interleaved ripple (Module 02's multi-phase rule) Stacked/multi-phase operation section (current sharing, phase interleave); output-voltage accuracy vs the ±1 % DS958 budget; differential remote-sense (VOSNS±) connections — sense at the VE2302 balls; I²C VOUT step size for margining at bring-up (Module 07)
Mid-current PoL bucks (1.0 V VCCO, 1.2 V AVTT, 0.88 V AVCC, 1.5 V AUX) TPS62830x family (3 A class, per rail) Small integrated-FET sync bucks off the 5 V bus; one per voltage group Output ripple vs fsw against the DS958 AC limits (10 mV p-p on AUX!); soft-start / EN threshold — these pins implement the sequence in step 5
Low-noise analog rails (GTYP AVCC cleanup / 1.5 V SMON) TPS746-Q1 1 A high-PSRR LDO with power-good — the buck-then-LDO pattern for jitter-critical GTYP supplies (Module 02) PSRR vs frequency curve at your upstream buck's fsw (not the 1 kHz headline!); output noise (µVRMS) vs the GTYP jitter budget; dropout voltage at load — confirms 1.0 V→0.88 V headroom; PG thresholds for the sequencing chain
3.3 V housekeeping (12 mA) TPS7B69-Q1 150 mA, 40 V-tolerant LDO straight off the input — alive before the bus converters Wide-VIN rating (40 V); quiescent current (always-on rail)
Rail monitoring & sequencing TPS389006-Q1 (+ TPS38700S sequencer option) 6-channel I²C-programmable UV/OV monitor supervising every group; drives POR_B (Modules 04 & 07) Threshold accuracy spec — must be much tighter than the ±1 % rails it polices; programmable UV/OV window & glitch filter; RESET/alert output behavior vs the VE2302's POR_B requirement
Alternative: PMIC route LP8769-Q1 Four-buck PMIC (5 A/20 A multiphase) with built-in NVM sequencing — the "multi-rail PMIC" architecture from Module 02 collapsing several discrete parts Per-buck current limits in multiphase configurations vs the 39 A core group; NVM sequence-slot programming

4 The resulting power tree

8–18 V input LM74910-Q1 ideal diode · UV/OV · OC LM25148-Q1 5 V / 12 A bus TPS62876-Q1 ×2 stacked · remote sense 0.8 V · 39 A core ② TPS62830x — 1.0 V / 3 A VCCO ① TPS62830x — 1.5 V / 1.1 A VCCAUX group ③ TPS62830x — 1.2 V / 1.3 A GTYP AVTT ④ buck 1.0 V TPS746-Q1 LDO GTYP AVCC 0.88 V ④ TPS7B69-Q1 — 3.3 V LDO Versal AI Edge XCVE2302 VCCINT · VCC_SOC · VCC_PMC VCC_PSFP · VCC_PSLP VCC_RAM · VCC_IO VCCO banks VCCAUX · VCCAUX_PMC · SMON GTYP AVTT / AVCC POR_B ← supervisor TPS389006-Q1 6-ch UV/OV monitor POR_B released only when all rails valid

PMP23227-style tree: protected 12 V → 5 V intermediate bus → PoL converters. Circled numbers = power-up groups (next step). GTYP AVCC uses the buck-then-LDO pattern for noise.

5 Sequencing per DS958

  • DS958's Power Supply Sequencing section is law: Versal requires the PMC-domain supplies (and PMC-bank VCCO) valid early, and POR_B may only be released after VCCAUX_PMC is stable (AMD answer record 000039045 covers the I/O behavior during ramp).
  • In the consolidated TI design the groups come up ① VCCO → ② 0.8 V core group → ③ VCCAUX group → ④ GTYP rails, implemented with EN/PGOOD chaining (Module 04) or the TPS38700S sequencer; the TPS389006-Q1 verifies every rail's window before the supervisor releases POR_B.
  • Monotonic-ramp rule (Module 04) applies to every group — verify each regulator's soft-start behavior into pre-biased outputs in its datasheet.
  • Margining bonus: TPS62876-Q1's I²C VOUT control lets you run DS958 corner testing (±5 %) at bring-up without soldering — Module 07's load-transient test, automated.

6 Design verification shortlist

  • PDN: Ztarget for the core group = 0.8 V × 1.5 % ÷ (0.33 × 39 A) ≈ 0.9 mΩ — run it through the Module 05 calculator; follow UG1506's decoupling table as the floor.
  • Thermal: TPS746 dropping 1.0 → 0.88 V at 0.7 A dissipates ~84 mW — trivial; the TPS62876 pair at 39 A is the real hotspot → check its RθJA/thermal design section and give it the copper.
  • Efficiency sanity: ~50 W out of an 18 V input → front-end + two conversion stages ≈ 85–90 % — confirmed by the PMP23227 test report (TIDT387) efficiency curves.
  • Bring-up: follow the Module 07 ritual; capture the 4-group sequence and archive it against DS958's requirements.

References

Every document used in this module. Datasheet links use the manufacturers' permanent URLs; always confirm you have the latest revision before sign-off.

# Document Publisher Link
[1] DS958 — Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics AMD docs.amd.com
[2] UG1506 — Versal Adaptive SoC Board System Design Methodology Guide AMD docs.amd.com
[3] UG1556 — Power Design Manager User Guide (PDM tool page) AMD docs.amd.com · tool
[4] AR 000039045 — Versal I/O behavior at power-up (answer record) AMD adaptivesupport.amd.com
[5] PMP23227 — Power delivery reference design for AMD Versal AI Edge (design page) TI ti.com/tool/PMP23227
[6] PMP23227 design files — schematic TIDMCR9 · BOM TIDMCS1 · test report TIDT387 TI schematic · BOM · test report
[7] SNVAA98 — Power Supply Design for AMD Versal AI Edge Series (application note) TI ti.com/lit/pdf/snvaa98
[8] TIDUFF9 — Power Supply Proof-of-Concept Design for Versal AI Edge Gen 2 (design guide) TI ti.com/lit/pdf/TIDUFF9
[9] LM74910-Q1 datasheet — ideal-diode front-end controller TI PDF · product page
[10] LM25148-Q1 datasheet — 42 V synchronous buck controller (5 V bus) TI PDF · product page
[11] TPS62876-Q1 datasheet — 25 A stackable buck (0.8 V core group) TI PDF · product page
[12] TPS746-Q1 datasheet — 1 A high-PSRR LDO (GTYP analog rails) TI PDF · product page
[13] TPS7B69-Q1 datasheet — 150 mA 40 V LDO (3.3 V housekeeping) TI PDF · product page
[14] TPS389006-Q1 datasheet — 6-channel I²C UV/OV supervisor (POR_B gating) TI PDF · product page
[15] LP8769-Q1 datasheet — four-buck PMIC alternative TI PDF · product page
[16] TPS62830x mid-current bucks and TPS38700S sequencer — exact variants per the PMP23227 BOM [6] TI see BOM
[17] ISLVERSALDEMO3Z — Renesas power management reference design for Versal (alternative tree) Renesas renesas.com
[18] Power tree for Versal AI Edge / Prime Gen 2 — minimum rails (alternative tree) Infineon infineon.com (PDF)
[19] Versal AI Edge (automotive) reference design (alternative tree) MPS monolithicpower.com
[20] VE2302 Carrier Card Hardware User Guide — a shipping board's power implementation to study Avnet avnet.com (PDF)
Same method, different silicon: [17]–[19] are validated alternative power trees from other vendors. Always re-run PDM [3] and re-verify every cited parameter against the current datasheet revision before committing a BOM.
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