Module 05 Plotly Calculator

PDN & Decoupling

The regulator handles milliseconds; everything faster is the capacitor network's job. Design it to an impedance target and the "how many caps?" argument answers itself.

Target impedance: the one number that sizes everything

If the fabric can step \( \Delta I \) of current and the rail may droop at most its tolerance share \( \Delta V \), then at every frequency where that step has energy the supply must look like less than:

\( Z_{target} = \dfrac{\Delta V}{\Delta I} = \dfrac{V_{rail} \cdot tol_{transient}}{\Delta I_{step}} \)

Example: VCCINT = 0.85 V, transient budget 1.5 % (12.75 mV), worst step 3 A → Ztarget ≈ 4.25 mΩ from ~1 kHz to ~100 MHz. Above that, on-package and on-die capacitance take over; below, the regulator loop holds the rail.

Shortcut for typical designs: the FPGA vendor's PCB design guide publishes a per-rail decoupling table (so many 100 nF, 4.7 µF, 100 µF per device). Use it as the floor; compute Ztarget yourself when your transient is unusual (heavy DSP bursts, big clock gating) or you're trimming BOM.

Interactive: build your capacitor network

Plotly

Adjust quantities and watch |Z(f)|. Each capacitor is modeled as series R-L-C (realistic ESR/ESL); parallel groups create the valleys — and the anti-resonance peaks between them.

Bulk 330 µF polymer (12 mΩ, 5 nH) 1
22 µF 0805 MLCC (4 mΩ, 1.2 nH) 4
100 nF 0402 MLCC (10 mΩ, 0.6 nH) 10
Ztarget (mΩ) 5

|Z| vs frequency (log–log). Red dashed line = Ztarget. Regulator (mΩ + µH behavior) dominates the left edge; spreading/plane inductance limits the right.

Anti-resonance: where one group's inductive rise crosses the next group's capacitive fall, their parallel combination peaks. Fixes: overlap the groups (more intermediate values), add controlled-ESR parts for damping, or accept the peak if it stays under Ztarget. Watch the peak move as you drag the sliders.

Placement & mounting: inductance is the enemy

  • 100 nF HF caps: as close to the BGA power balls as manufacturing allows — backside directly under the ball field is best; every mm of trace ≈ 1 nH that blunts the cap.
  • Via discipline: two vias per pad (or via-in-pad) for HF caps; a single long thermal-relief trace can double mounted inductance.
  • 22 µF mid caps: ring around the BGA within ~1–2 cm.
  • Bulk: anywhere on the rail near the regulator — its job is charge storage, not speed.
  • Planes: a solid power pocket/plane per major rail with a tight ground plane above/below makes the interconnect itself a low-ESL capacitor — this is what actually delivers current above ~50 MHz.
  • Follow the vendor's per-pin vs per-region guidance — modern large BGAs are per-region (the plane does per-pin's old job).

Key takeaways

  • Ztarget = ΔV/ΔI — one formula sizes the entire network.
  • Mix decades of capacitor values; overlap groups to tame anti-resonance.
  • Use DC-bias-derated capacitance (Module 02) in every calculation.
  • Mounted inductance (pads + vias + trace) matters more than the cap's own ESL — placement is design.
The full theory — spreading inductance, plane resonances, VRM models — lives in the SI Academy's Power Integrity module.
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