Module 03

How to Connect: Building the Power Tree

From one input connector to nine happy rails: cascade vs parallel, which rails may legally share a regulator, and where a ferrite bead is enough isolation — all on one worked example.

Topology: input → intermediate → point-of-load

With a 12 V (or 24 V) input, don't buck every rail straight from the input — duty cycles get tiny and efficiency suffers. The standard pattern is an intermediate bus (5 V or 3.3 V) feeding point-of-load (PoL) bucks and LDOs:

  • Parallel from input: fine for 12 V→3.3 V and 12 V→1.0 V synchronous bucks with reasonable duty cycles.
  • Cascade: 12 V→1.8 V→LDOs for analog rails; watch that the intermediate rail's current includes everything downstream.
  • Sharing with companions: DDR VDDQ can share the FPGA's matching VCCO bank rail; clock chips can share VCCAUX's 1.8 V — but transceiver rails share with nobody.

Rail-merging rules

Merge candidate Verdict Condition
VCCINT + VCCBRAM Usually yes Same voltage; check the vendor's "supply consolidation" table
VCCAUX + VCCADC Often yes Through a ferrite + local decoupling for the ADC side
VCCO banks at same voltage Yes Unless one bank is a noisy switching interface next to a quiet one
VCCINT + VMGTAVCC (same 1.0 V!) No Transceiver jitter budget dies from core noise — separate regulator/LDO
VMGTAVCC + VMGTAVTT No Different voltages and both noise-critical; dedicated LDOs
Ferrite bead isolation is not free: a bead + local caps forms a resonant LC. Used on quiet, low-current analog rails it's fine; on a rail with transient load steps it can amplify noise at resonance. Damp it (small series R or lossy bead) and never put one in a high-current core path — the DC drop breaks your tolerance stack.

Worked example: Zynq-7020 power tree

12 V input Buck 1.0 V / 4 A fast loop + remote sense VCCINT + VCCBRAM ① Buck 1.8 V / 2.5 A aux + LDO feed VCCAUX + VCCADC ② LDO 1.0 V LN <100 µV RMS VMGTAVCC ④ LDO 1.2 V LN termination VMGTAVTT ④ Buck 1.5 V / 2 A VCCO (DDR3) + VDDQ ③ Buck 3.3 V / 2 A VCCO (3.3 V banks) ③ Zynq-7020 XC7Z020-CLG484 ① core first ② aux second ③ I/O third ④ MGT rails last power-down: reverse order

Five regulators, one supervisor (not shown), circled numbers = power-up order (Module 04). Transceiver rails come off the 1.8 V intermediate through low-noise LDOs — never off VCCINT.

Connection rules that save respins

  • Every FPGA power ball connects. No floating VCCO on "unused" banks — tie unused banks per the datasheet (usually to a valid rail) or configuration may fail.
  • Remote sense from the VCCINT regulator to a sense point under the FPGA; route as a quiet Kelvin pair (Module 06).
  • PGOOD outputs are open-drain — pull them up to a rail that exists before they're read (a classic chicken-and-egg bug in sequence chains).
  • Enable-pin thresholds: check EN VIH against the driving rail; a 1.0 V PGOOD can't reliably enable a buck whose EN needs 1.2 V.
  • VBATT: if unused, tie per datasheet (usually GND or VCCAUX via resistor) — don't leave it floating.
  • Fit 0 Ω links (or current-loop pads) in each rail for bring-up current measurement — Module 07 will thank you.

Key takeaways

  • Intermediate-bus topology keeps duty cycles and efficiency sane.
  • Merge rails only where the vendor's consolidation table says you may; transceiver rails never merge.
  • Ferrite isolation needs damping and belongs only on quiet analog rails.
  • The power tree diagram (with sequence numbers) is a deliverable — put it on schematic page 1.
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