Power Integrity Basics
Master PDN impedance analysis, decoupling capacitor selection, target impedance methodology, and anti-resonance phenomena for robust power delivery networks.
What is Power Integrity?
Power Integrity (PI) is the discipline of ensuring that every IC on a PCB receives clean, stable voltage within its specified tolerance. When a processor, FPGA, or ASIC switches state, current demand can spike by tens of amperes within nanoseconds. The Power Distribution Network (PDN) must supply this current without causing voltage to droop below the IC's minimum operating level.
Poor power integrity causes bit errors, timing failures, jitter, and in extreme cases, permanent IC damage. Unlike signal integrity which focuses on individual traces, power integrity concerns the entire plane-capacitor network that feeds every power pin simultaneously.
Why Power Rails Fail
Real-World Power Integrity Challenges
Ztarget = 1.4 mΩ
Ztarget = 12 mΩ
Ztarget = 0.5 mΩ
Ztarget = 11 mΩ
The PDN Chain
A Power Distribution Network (PDN) is the complete path from the voltage regulator module (VRM) to the IC's power pins. Each element in this chain has unique impedance characteristics that dominate at different frequency ranges. Together, they must maintain a flat, low-impedance profile from DC to several GHz.
The PDN is a distributed RLC network. At low frequencies (<1 kHz), the VRM provides current. Mid-frequency demands (1 kHz–10 MHz) are supplied by bulk and ceramic capacitors. High-frequency current (>10 MHz) is served by on-die capacitance and the interplane capacitance of the PCB stackup itself.
PDN Components & Frequency Ranges
PDN Equivalent Circuit: From Source to Load
The Target Impedance Equation
Target impedance defines the maximum allowable PDN impedance to keep voltage ripple within specification. It is the single most important metric in power integrity design:
The PDN impedance must remain below Ztarget across the entire frequency range from DC to the maximum transient bandwidth (BW ≈ 0.35/trise). If impedance exceeds this limit at any frequency, voltage will violate tolerance during transient loading.
Design Implications
Target Impedance Examples
| Application | VDD | Ripple % | Itrans | Ztarget | Difficulty |
|---|---|---|---|---|---|
| MCU I/O (3.3V) | 3.3V | 5% | 1A | 165 mΩ | Easy |
| DDR4 VDD (1.2V) | 1.2V | 5% | 5A | 12 mΩ | Moderate |
| FPGA Core (0.85V) | 0.85V | 5% | 30A | 1.4 mΩ | Hard |
| CPU VCORE (1.0V) | 1.0V | 5% | 100A | 0.5 mΩ | Extreme |
Real Capacitor Model
A real capacitor is not an ideal capacitance — it is a series RLC circuit. The Equivalent Series Resistance (ESR) sets the minimum achievable impedance, while Equivalent Series Inductance (ESL) causes impedance to rise above the self-resonant frequency (SRF).
At the self-resonant frequency, XL = XC and impedance drops to ESR alone. Below SRF the cap behaves capacitively; above SRF it behaves inductively.
Key Parameters
The Anti-Resonance Problem
When two capacitors with different SRFs are placed in parallel, an anti-resonance peak forms between their resonant frequencies. At this frequency, one cap is inductive and the other is capacitive — they form a parallel LC tank that creates a high-impedance peak.
This peak can exceed the target impedance and cause voltage violations even though each capacitor alone meets spec at its SRF. Anti-resonance is the primary challenge in multi-cap PDN design.
Mitigation Strategies
Scenario: Xilinx Kintex-7 FPGA Core Rail
You are designing the VCCINT (1.0V core) PDN for a Kintex-7 325T FPGA. The device has:
- VDD = 1.0V, tolerance = ±5% (Vmin = 950mV)
- Peak transient current: 25A (during configuration + DSP burst)
- Fastest edge rate: 200 ps
- VRM bandwidth: 80 kHz, VRM output impedance: 2 mΩ
- Available PCB layers: 8-layer stackup, 62-mil total thickness
Task 1: Calculate Ztarget
Given: VDD=1.0V, Ripple=5%, Itrans=25A
Ztarget = (1.0 × 0.05) / 25 = 2.0 mΩ
This is a very aggressive target — sub-2mΩ requires careful multi-cap strategy.
Task 2: Determine BW Coverage
BW = 0.35 / trise = 0.35 / 200ps
BW = 1.75 GHz
PDN must be below 2 mΩ from DC to 1.75 GHz. PCB plane capacitance and on-die caps handle >100 MHz.
Task 3: Recommended Capacitor Strategy
ESR: 5mΩ
Coverage: 1k–100kHz
ESR: 3mΩ
Coverage: 100k–10MHz
ESL: 0.3nH
Coverage: 1M–100MHz
Plane cap: ~5nF
Coverage: >100MHz
Ready to complete this module?
Mark this module as complete once you have reviewed all sections, finished the design exercises, and passed the knowledge check.