Module 07 Bring-up

Bring-up & Verification

Never let a fresh board meet a full-power supply on faith. Twenty minutes of disciplined bring-up catches what would otherwise be a week of "why won't it configure?"

Before first power

  • Ohm every rail to ground and rail-to-rail — catch solder bridges cold. Record the values (a "healthy" VCCINT reads tens of ohms, not ∞, due to the FPGA itself).
  • Verify regulator feedback networks against the schematic — a swapped divider resistor is the classic overvoltage killer.
  • If your 0 Ω current links (Module 03) are fitted, note which rails you can isolate.
  • Visual: caps of the right size in the right spots, polarity of any polymers, no missing FB parts.

The first power-up ritual

  1. Current-limited bench supply into the input — start with the limit at ~20 % above expected idle current. A limit hit = stop and investigate, nothing burns.
  2. Set-points: DMM every rail at its sense point (not the regulator output cap). All within tolerance before anything else happens.
  3. Sequence capture: 4-channel scope on VCCINT/VCCAUX/VCCO/RESET; single-shot trigger on the input. Verify order, ramp times inside the datasheet window, and monotonicity. Archive the screenshot — it's your golden reference forever.
  4. Configuration: load a bitstream; watch DONE go high. Then re-measure rails under the real design's load.
  5. Ripple: measure with tip-and-barrel (no ground clip loop!), 20 MHz bandwidth limit for the regulator-band number, full bandwidth for a look at switching spikes. Compare against the stack budget from Module 01.
  6. Load transient: toggle the heaviest logic block (or use an on-fabric load generator design) while scoping VCCINT — droop must stay inside the transient budget.
  7. Thermal survey: IR camera or thermocouples on every regulator and the FPGA at max load, max ambient if you can chamber it.

In-system monitoring

  • XADC / SYSMON: the FPGA's internal ADC reads VCCINT, VCCAUX, VCCBRAM and die temperature for free — expose them in your design's status registers and log them in production units.
  • PGOOD aggregation: AND all PGOODs into a status LED and a supervisor input; a field return that "sometimes reboots" is diagnosed in seconds if you can see which rail flickers.
  • PMBus telemetry (if you used a manager IC): per-rail voltage/current/fault logs — invaluable for fleet debugging.

Failure signatures

Symptom Likely cause Check
Won't configure (DONE never rises) Sequence/ramp violation; VCCAUX missing; non-monotonic VCCINT Sequence capture vs datasheet; INIT_B state
Configures, crashes under load VCCINT droop beyond budget (PDN or regulator transient) Scope VCCINT during the crash workload
Transceiver bit errors / link flaps MGT rail ripple/noise; shared-rail contamination µV-level ripple on VMGTAVCC; eye scan trend vs load
Random BRAM/logic corruption VCCBRAM sag; local hot spot XADC logs vs failure times; IR camera
Reboots at power-on only when cold/hot Soft-start vs supervisor timing race at temperature Chambered sequence captures at extremes
Input supply current limit at plug-in Inrush (all bulk caps at once) — or a real short Stagger soft-starts; inrush limiter on input

Key takeaways

  • Current-limited first power, always; set-points before sequence, sequence before configuration.
  • The archived sequence screenshot is a deliverable of the design.
  • Ripple technique matters: tip-and-barrel, both bandwidths, at the load.
  • Design in observability — XADC + PGOOD LEDs turn field mysteries into log entries.
← Layout & Thermal Next: Checklist & FAQ →