Why FPGA Power is Different
An MCU wants one rail and 100 mA. An FPGA wants nine rails, three of them within ±3 %, brought up in the right order, with transients measured in amps per microsecond. Here's the map before we start walking.
The rail map
| Rail family | Typical voltage | Feeds | Current | Sensitivity |
|---|---|---|---|---|
| VCCINT | 0.7 – 1.0 V | Core logic fabric | Highest (1 – 30+ A) | ±3 % total — the hardest rail |
| VCCBRAM | = VCCINT (usually) | Block RAM | Low–mid | Sag ⇒ memory corruption |
| VCCAUX | 1.8 V | Config logic, clock mgmt. | Low–mid | Needed before configuration |
| VCCO (per bank) | 1.2 – 3.3 V | I/O banks | Design-dependent | Set by I/O standard (DDR bank ≠ LVCMOS bank) |
| VMGTAVCC / AVTT | 0.9 / 1.2 V | Transceivers (GTX/GTH…) | Mid | Noise-critical — mV of ripple = bit errors |
| VCCADC / VREF / VBATT | 1.8 V / ext / coin cell | XADC, references, key storage | mA | Quiet analog supply |
Design-dependent current — same chip, 10× difference
Unlike a CPU, an FPGA's current depends on your bitstream: logic utilization, clock frequencies, toggle rates and I/O loading. A design at 30 % utilization / 100 MHz and one at 90 % / 400 MHz can differ by an order of magnitude on VCCINT. Three consequences:
- You must run the vendor estimator (AMD XPE / Intel EPE) with your real design parameters — copying another board's supply is how boards die at 80 % utilization.
- Inrush & configuration current: at power-up, before your logic even runs, configuration draws a current spike — datasheets specify minimum supply current capability just to configure.
- Transients: a clock-enable flipping half the fabric on in one cycle creates di/dt steps of amps per microsecond — this is what the PDN (Module 05) must absorb, not the regulator.
The tolerance stack
VCCINT at "0.85 V ±3 %" gives you a total window of ±25.5 mV — and everything must fit inside it:
Set-point accuracy + ripple + load-transient droop must all stack inside the datasheet window. This stack drives regulator choice (Module 02) and PDN design (Module 05).
Rail budget worksheet
CalculatorEnter your estimator outputs; get total power, per-rail margined current, and the input current your source must supply (assumes 90 % average conversion efficiency).
| Rail | Voltage (V) | Current (A) | Margin % | Margined I | Power |
|---|---|---|---|---|---|
| VCCINT | — | — | |||
| VCCAUX | — | — | |||
| VCCO (all banks) | — | — | |||
| VMGTAVCC | — | — | |||
| VMGTAVTT | — | — | |||
| Totals | — | — | |||
| Input current @ 12 V, η = 90 % | — | ||||
Key takeaways
- Map every datasheet rail to a role: core, aux, I/O, analog/transceiver, housekeeping.
- Current is bitstream-dependent — run XPE/EPE with real parameters, then add 20–30 %.
- The ±3 % window is a stack: set-point + ripple + droop. Budget all three explicitly.
- Transceiver rails are a different discipline: treat them as analog supplies.