Power Your FPGA Right
from Rail Map to Verified Bring-up
An FPGA datasheet lists nine rails, ±3 % tolerances, sequencing rules and amp-level transients — this course turns that into a working power tree. Component selection, connection topologies, sequencing, PDN decoupling and bring-up, with animated diagrams, Plotly charts and three design calculators.
Course Modules
Follow the design flow in order — it mirrors how you'd actually build the supply.
Why FPGA Power is Different
The rail map (VCCINT → VMGT), design-dependent currents, vendor estimators, and the tolerance stack that rules everything.
Selecting Components
Discrete vs PMIC vs module, buck and LDO selection, inductor ripple math, and the ceramic DC-bias trap — with a worked Zynq parts table.
Building the Power Tree
Input to point-of-load topologies, which rails may share a regulator, and the full annotated Zynq-7000 power tree.
Power Sequencing
Why order matters, required up/down sequences, ramp rates, and three implementation patterns — animated PGOOD handoff included.
PDN & Decoupling
Target impedance from first principles and an interactive capacitor-mix impedance plot — see anti-resonance before you build it.
Layout & Thermal
Regulator placement, plane strategy, remote sense routing, and an LDO junction-temperature quick-check calculator.
Bring-up & Verification
First power-up ritual, sequence capture, ripple measurement technique, XADC/PGOOD monitoring, and the failure-signature table.
Checklist & FAQ
Vendor references, the printable 15-point power design review checklist, and answers to the questions everyone asks.
Worked Example: Versal SoC
A complete VE2302 power design with real part numbers — LM74910, LM25148, TPS62876 ×2, TPS746, TPS389006 — and the exact datasheet parameter to verify at each step.