Standards, Variants & the Design Checklist
The cousins you'll meet in datasheets — SMBus, PMBus, I3C — and the 15-point checklist that catches 95 % of I2C design escapes before layout review ends.
SMBus vs I2C — close, but not the same
| Property | I2C | SMBus |
|---|---|---|
| Clock range | 0 (DC) – 3.4 MHz | 10 kHz – 100 kHz (min speed exists!) |
| Timeout | None — can stretch forever | 35 ms — bus self-heals |
| Logic levels | Ratiometric (30 %/70 % of VCC) | Fixed thresholds (0.8 V / 2.1 V) |
| Extra signal | — | SMBALERT# open-drain interrupt line |
| Protocol layer | None mandated | Defined commands, PEC (CRC-8) option |
| Typical home | Embedded peripherals | PC/server management, batteries, VRMs |
PMBus is SMBus plus a standardized command set for power converters (VOUT_COMMAND, READ_TEMPERATURE, fault logs). Electrically follow SMBus rules; the value is the interoperable command vocabulary.
I3C in one paragraph
MIPI I3C keeps two wires and backward compatibility with I2C targets, but switches to push-pull signaling at up to 12.5 MHz SDR, adds in-band interrupts (no more INT pins), dynamic address assignment (no more A0 straps), and hot-join. The catch: controller and target support is still concentrated in sensors/mobile, and the electrical design rules are completely different — your pull-up math from Module 03 does not carry over. If your platform offers it for a dense sensor cluster, evaluate it; otherwise I2C remains the default for years yet.
The 15-point I2C design review checklist
Tick items as you review — ticks are just visual (nothing is saved). Use the Print button for a hard copy for design reviews.
FAQ
What pull-up resistor should I use for I2C?
Calculate it: Rmin = (VCC − 0.4 V)/3 mA, Rmax = tr/(0.8473·Cbus), pick an E24 value between them. For a typical 3.3 V, 400 kHz bus around 150 pF, 2.2 kΩ is the classic answer — but use the calculator with your real capacitance.
How many devices can share one I2C bus?
The protocol allows 112 addresses, but the electrical limit arrives first: 400 pF of total bus capacitance — typically 10–20 devices with realistic routing. Buffers/muxes extend this indefinitely by segmenting.
Can I2C have two masters?
Yes — clock synchronization and lossless arbitration are built into the spec (Module 05). In practice verify both controllers' silicon and drivers handle arbitration loss; many designs are better restructured with a single bus owner.
Why does my I2C bus hang?
Usually a target left mid-byte holding SDA low after a controller reset. Recover by bit-banging up to 9 SCL pulses then a STOP (Module 07). Prevent it with boot-time recovery and transaction timeouts.
Do SDA and SCL need the same pull-up value?
Use matched values. SCL only needs to meet rise time from the controller's perspective, but keeping both identical avoids skewed timing margins and simplifies BOM — there's no benefit to mixing.
Can I run I2C through a cable between boards?
Short cables (tens of cm) with a ground between the lines work if you count the capacitance. Beyond that, put a buffer at the connector, or use a differential extender (PCA9615) for meters (Module 06).
You made it 🎉
You can now size pull-ups from first principles, architect single- and multi-master buses, and debug the classic failures from a scope shot. Keep going: the Signal Integrity Academy turns the rise-time intuition you built here into full transmission-line design, and the ESD training hardens your connectors properly.