Module 03 Plotly Calculator

Selecting Pull-up Resistors

The most-asked I2C design question, answered properly: two formulas, one design window, and an interactive calculator. Too weak and your edges are slow; too strong and your lows aren't low. Let's find the window.

Why the value matters

A falling edge is fast — a transistor yanks the line down. A rising edge is passive: the pull-up must charge the entire bus capacitance \(C_{bus}\) through an RC curve. Meanwhile every LOW burns \(V_{CC}/R_p\) of current through the pulling device, which must still keep the line under \(V_{OL(max)}\) (0.4 V). Hence a window:

  • R too large → rise time \(t_r\) exceeds spec → data corruption at speed, works "sometimes".
  • R too small → device can't sink enough current → \(V_{OL}\) creeps up, noise margin gone, extra power.

Lower limit: Rmin (sink current)

\( R_{min} = \dfrac{V_{CC} - V_{OL(max)}}{I_{OL}} \)

With the standard values \(V_{OL(max)} = 0.4\,\text{V}\) and \(I_{OL} = 3\,\text{mA}\):

VCC Rmin
1.8 V (1.8 − 0.4) / 3 mA ≈ 467 Ω
3.3 V (3.3 − 0.4) / 3 mA ≈ 967 Ω
5.0 V (5.0 − 0.4) / 3 mA ≈ 1.53 kΩ

Upper limit: Rmax (rise time)

The spec measures \(t_r\) between 30 % and 70 % of \(V_{CC}\). Solving the RC charging equation between those two points gives \(t_r = R_p C_{bus}\,(\ln 0.7^{-1}... )\) — the constant works out to 0.8473:

\( R_{max} = \dfrac{t_r}{0.8473 \cdot C_{bus}} \)
Mode tr max Rmax @ 100 pF Rmax @ 200 pF Rmax @ 400 pF
Standard 100 kHz 1000 ns 11.8 kΩ 5.9 kΩ 2.95 kΩ
Fast 400 kHz 300 ns 3.54 kΩ 1.77 kΩ 885 Ω ⚠
Fast+ 1 MHz 120 ns 1.42 kΩ 708 Ω ⚠ — ⚠
⚠ Where \(R_{max} < R_{min}\) the window has closed: the bus is too capacitive for that speed. Fix it by lowering Cbus, dropping the speed, or adding a bus buffer (Module 04).

Interactive: watch the rising edge

Plotly

SDA rising edges for four pull-up values at 3.3 V — drag the Cbus slider and watch which resistors stop meeting Fast-mode's 300 ns limit (dashed line at 70 % VCC).

RC rise curves: v(t) = VCC(1 − e−t/RC). The circles mark where each curve crosses 70 % VCC — the end of the measured rise.

Interactive: the design window

Plotly

The full picture: Rmax falls as bus capacitance grows, while Rmin stays flat. Your pull-up must live in the shaded region. Note the Fast+ window slamming shut just past 140 pF.

Valid pull-up region vs Cbus at 3.3 V (IOL = 3 mA). Log-scaled Y axis.

Estimating Cbus

  • Each device pin: ~10 pF max per the spec (typ. 3–7 pF).
  • PCB trace: ~1 pF/cm on outer layers (more over thin dielectrics).
  • Connector + cable: 30–100 pF/m — cables eat your budget fastest.
  • Spec ceiling: 400 pF (Sm/Fm), 550 pF (Fm+).
Example: 6 devices (60 pF) + 25 cm of trace (25 pF) + controller pin (10 pF) ≈ 95 pF → comfortably inside Fast-mode with 2.2 kΩ.

Pull-up calculator

Interactive
Rmin —
Rmax —
Recommended E24 value —
Rise time with that value —
Static power per line (LOW) —

Practical rules

Situation Starting value
3.3 V, 100 kHz, small bus 4.7 kΩ – 10 kΩ
3.3 V, 400 kHz (typical design) 2.2 kΩ
3.3 V, 1 MHz Fast+ 1 kΩ
Battery-powered, slow bus 10 kΩ (accept slow edges)
  • One pull-up pair per bus — never per device. Duplicated pull-ups combine in parallel and can breach Rmin.
  • Place them near the controller or electrical center of the bus.
  • Internal MCU pull-ups (30–50 kΩ) are not enough for anything beyond one device at 100 kHz on a tiny board.
  • SDA and SCL get the same value; keep them matched.
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