Multiple Masters, One Bus
I2C was designed from day one to let several controllers share the same two wires — thanks to the wired-AND, they can even collide mid-byte and nobody's data gets corrupted. Here's how that works, and why you should still think twice.
When multi-master actually appears
- An application MCU and a wireless SoC sharing one sensor set.
- A supervisor/BMC and a host CPU sharing management devices (very common in servers — via SMBus).
- Hot-swap backplanes where each card's controller talks on a shared bus.
Multi-master, multi-slave: both MCUs can initiate transfers to any target on the same wires.
Clock synchronization
If both controllers clock simultaneously, SCL becomes the AND of their clocks: the line only rises when every controller has released it, and any controller can hold the low phase longer. Result: the bus automatically runs at the slowest participant's pace — no negotiation needed. This is the same mechanism as clock stretching, applied between controllers.
Arbitration: losing without corrupting
AnimatedTwo controllers can START at the same instant. Each transmits its bits while reading the bus back. Writing a 1 means releasing the line — so if the other controller writes a 0, the line stays low, and the "1" controller reads back a 0: it just lost arbitration. It backs off immediately and mid-bit. The winner never notices; its transfer proceeds intact.
Bit-by-bit arbitration. The bus (wired-AND) follows whoever writes 0. The moment A's sent bit ≠ read-back bit, A silently bows out; B's frame is untouched. Lower addresses therefore win arbitration.
Design requirements for real multi-master
- Silicon: every controller's I2C peripheral must support arbitration-loss detection and clock sync (check the reference manual — not all do, and bit-banged controllers never do).
- Firmware: on arbitration loss, the driver must retry later — and cope with being addressed as a target mid-retry.
- Repeated START discipline: multi-message transactions must use Sr, or another master can sneak in between your write and read.
- All controllers open-drain: one push-pull SCL driver destroys the whole scheme (and possibly a port pin).
- Timeouts everywhere: a hung target blocks all masters, so every controller needs bus-recovery logic (Module 07).
Safer alternatives
| Alternative | How it works | Best when |
|---|---|---|
| Single owner + mailbox | MCU A owns the bus; MCU B requests data over UART/SPI/shared memory | You control both firmwares |
| Bus mux + request GPIO | An analog switch hands the whole bus to one controller at a time | Coarse-grained sharing (e.g. boot-time programming) |
| Dual-port target devices | Some PMICs/EEPROMs expose two independent I2C ports | Only 1–2 shared devices |
| Accept multi-master (SMBus) | Follow SMBus rules — timeouts make failure modes bounded | Server/BMC-style management buses |
Key takeaways
- Wired-AND makes collisions harmless: arbitration is lossless and the winner's frame survives untouched.
- A controller loses the moment it reads 0 while sending 1 — then it must retry and be addressable as a target.
- Verify peripheral + driver support before committing; it's the weakest link.
- If the architecture allows, prefer a single bus owner — multi-master correctness is mostly a firmware tax.