Module 07

Robustness, Protection & Bring-up

The bus that works on the bench and hangs in the field: ESD events, stuck targets, hot-plugged cables, marginal rise times. Design for recovery, then learn to read the scope like a story.

ESD & transient protection

  • Any SDA/SCL reaching a user-accessible connector gets a TVS diode array at the connector, referenced to chassis/board ground per your grounding scheme.
  • Choose low-capacitance TVS parts (< 10 pF/line, ideally < 3 pF) — protection capacitance counts against your 400 pF budget like everything else.
  • Working voltage ≥ bus rail; unidirectional parts give lower clamping for a ground-referenced bus.
  • Series resistors (Module 06) add a second line of defense for the IC pins behind the TVS.
  • Internal-only buses on a small board generally don't need discrete ESD parts — the IC's own HBM rating covers assembly handling.
System-level ESD levels, test methods and layout for protection parts are covered in depth in the ESD training.

Bus lock-up and the 9-clock recovery

Field failure #1

If the controller resets mid-read, a target can be left holding SDA low, waiting for a clock that never comes. The bus is now dead — every START attempt fails because SDA won't rise. No amount of controller resetting fixes it; the target has to finish its byte.

SCL SDA stuck low — target mid-byte target releases ✓ controller sends STOP bus idle again

Recovery: bit-bang up to 9 SCL pulses (a full byte + ACK slot) until SDA floats high, then generate a STOP. Do this in firmware at every boot, before enabling the I2C peripheral.

  • Firmware: boot-time recovery routine + transaction timeouts (SMBus specifies 35 ms — a good default).
  • Hardware options: route SDA/SCL to GPIO-capable pins so recovery is possible; for high-reliability systems add a bus-monitor/buffer with automatic disconnect, or power-switch the targets so you can hard-reset them.

Hot-plugging

Plugging a live module onto a live bus injects a capacitive glitch that can corrupt an in-flight transfer — or worse, power the module through its ESD diodes via SDA/SCL before its rail comes up. If modules must hot-plug, use a buffer with pre-charge and idle-detect (PCA9511-class hot-swap buffers) that only connects the segment when the bus is idle, and sequence power before signals in the connector pinout (longer power pins).

Reading the scope: failure signatures

What you see What it means Fix
Rounded, saggy rising edges Rp too big or Cbus too big Recalculate (Module 03); buffer or slow down
LOW level well above 0 V (> 0.4 V) Rp too small, or duplicated pull-ups in parallel Audit every module for stray pull-ups
Address sent, 9th bit high (NACK) Nobody home: wrong address / unpowered / wrong bus Check the 7-bit vs 8-bit address trap (Module 02)
SDA permanently low Locked-up target (or solder bridge) 9-clock recovery; check with bus powered down
SCL stays low forever after ACK Clock stretching that never ends Timeout + recovery; check target errata
Glitches on SDA aligned with SCL edges Crosstalk (Module 06) Spacing/return path; slow the edge with series R
Works cold, fails warm (or vice versa) Marginal rise time drifting with temperature You're at the window edge — move Rp toward the middle
Bring-up ritual: (1) scope both lines idle — must sit at VCC; (2) one address ping — check ACK and measure tr and VOL at the farthest device; (3) then, and only then, bring up firmware. A ₹2,000 logic analyzer decodes the rest.

Key takeaways

  • TVS at every external connector; low-capacitance parts only.
  • Bus lock-up is a when, not an if — ship the 9-clock recovery in every product.
  • Hot-plug needs a purpose-built buffer, not hope.
  • Three scope measurements (idle level, tr, VOL + ACK) validate the whole electrical design.
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