One Master, Many Slaves
Multi-drop is I2C's whole reason to exist — but every added device costs an address, some capacitance, and a little noise margin. Here's how to spend that budget deliberately.
The multi-drop topology
Daisy-chained multi-drop bus: every device taps the same two wires; exactly one pull-up pair serves them all.
- Route as a daisy chain with short taps — avoid a star of long stubs.
- Every device adds ~10 pF; track your running total against the 400 pF budget.
- All devices must share a common ground and compatible logic levels (or be shifted — below).
Address planning & conflicts
Build an address map in the schematic phase, not at bring-up. Many parts offer address-select pins (A0–A2 strapped high/low) giving 2–8 variants of a base address.
| Conflict fix | How | Cost / catch |
|---|---|---|
| Address pins | Strap A0–A2 differently per duplicate part | Free, but only 2–8 copies |
| Different part variant | Order the -B version with another base address | BOM management |
| I2C multiplexer / switch | TCA9548A-style: 1 upstream bus → up to 8 downstream channels | ~₹80; the mux itself uses an address; enables per-channel voltage too |
| Second bus | Use another MCU I2C peripheral | Pins; firmware handles two buses |
A mux solves the classic "four identical sensors, one address" problem — select a channel, talk, deselect.
Bus loading: hitting the 400 pF wall
Symptoms of an over-capacitive bus: rounded rising edges, works at 100 kHz but not 400 kHz, marginal ACKs from the far end. Options, in order of preference:
- Shorten routes / remove connectors from the main bus.
- Drop a speed class (often free if traffic is light).
- Bus buffer/repeater (PCA9515/9517-style): splits the bus into two independently loaded segments, each with its own pull-ups and its own 400 pF budget. Also isolates a hot-pluggable or off-board segment.
Mixed voltages: the MOSFET level shifter
A 1.8 V sensor on a 3.3 V bus needs level shifting on both lines. The classic bidirectional circuit (NXP AN10441) is one N-MOSFET per line, gate tied to the low rail:
Low side low → FET conducts → high side pulled low. High side low → body diode + FET pull the low side down. Both directions work with no control signal.
Do's and don'ts
| ✓ Do | ✗ Don't |
|---|---|
| One pull-up pair per electrical bus segment | Fit "just in case" pull-ups on every module (parallel Rp breaks Rmin) |
| Document the address map in the schematic | Discover conflicts at bring-up |
| Daisy-chain with short taps | Star topology with four 20 cm stubs |
| Buffer off-board / hot-plug segments | Run the raw bus through a long cable to a daughtercard |
| Check every device's VIH against the bus rail | Assume a "5 V tolerant" pin also outputs valid 5 V highs |