Module 01

What is I2C?

Two wires, dozens of devices, one elegant trick: open-drain drivers pulling against shared resistors. Understand this and everything else about I2C — pull-up sizing, arbitration, bus hangs — follows naturally.

The two-wire bus

I2C (Inter-Integrated Circuit, "I-squared-C") is a two-wire, synchronous, half-duplex, multi-drop serial bus invented by Philips (now NXP) in 1982. Every device shares the same two lines:

  • SDA — Serial Data. Carries address and data bits, both directions.
  • SCL — Serial Clock. Generated by the controller (master); targets (slaves) can hold it low to slow things down.

One controller initiates every transfer and addresses one of up to ~112 usable targets. Sensors, EEPROMs, RTCs, PMICs, GPIO expanders, touch controllers — if it's a low-speed peripheral, it probably speaks I2C.

Terminology: the specification now uses controller/target in place of the older master/slave. This course uses both interchangeably — datasheets you'll read use both too.

Open-drain drivers & the wired-AND bus

Animated

No I2C device ever drives a line high. Each pin is an open-drain transistor that can only pull the line low or release it. The shared pull-up resistor is the only thing that ever creates a logic 1 — which is why pull-up sizing (Module 03) matters so much.

VCC Rp SDA HIGH (released) → LOW (pulled) → HIGH Dev A releases Dev B pulls LOW Dev C releases

Open-drain bus: the pull-up creates the HIGH; any device can create a LOW. Watch Dev B periodically pull the whole line down.

Because a low always wins, the bus behaves as a wired-AND: the line is high only if every device releases it. This one property enables three signature I2C features — ACK (target pulls SDA low to say "got it"), clock stretching (target holds SCL low to say "wait"), and multi-master arbitration (Module 05).

Speed classes

Mode Max SCL Max rise time tr Typical use
Standard (Sm) 100 kHz 1000 ns Default. Fine for config registers, RTCs, slow sensors.
Fast (Fm) 400 kHz 300 ns The real-world workhorse — most modern designs run here.
Fast+ (Fm+) 1 MHz 120 ns Higher-bandwidth sensors; needs strong pull-ups (~1 kΩ).
High-Speed (Hs) 3.4 MHz (current-source assisted) Rare; special signaling, limited device support.
Ultra-Fast (UFm) 5 MHz push-pull, write-only Unidirectional variant (LED controllers); not a shared bus.
Rule of thumb: design for Fast-mode (400 kHz) unless a device forces you slower. The speed limit in practice is almost never the silicon — it is the RC rise time of your bus (Module 03).

I2C vs SPI vs UART

I2C SPI UART
Wires 2 (shared by all) 3 + 1 CS per device 2 per link (TX/RX)
Topology True multi-drop, multi-master capable Star (CS per target) Point-to-point
Speed 0.1–3.4 MHz (usually ≤1 MHz) 10–100+ MHz Usually ≤ 3 Mbaud
Addressing In-band (7/10-bit) Hardware CS lines None
Flow control ACK + clock stretching None built in Optional RTS/CTS
Weak spot Speed, bus hangs, capacitance limit Pin count, no ACK Only two endpoints
Choose when… Many slow peripherals, few pins Fast streaming (ADCs, flash, displays) Two boards / debug console

Key takeaways

  • I2C = two shared wires (SDA, SCL), one controller talking to many targets.
  • Nothing drives high — pull-up resistors create every logic 1. The bus is a wired-AND.
  • ACK, clock stretching, and arbitration all fall out of the open-drain trick.
  • 400 kHz Fast-mode is the practical default; RC rise time is the real speed limit.
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