Module 02

Protocol Essentials

Just enough protocol to design hardware well: how transfers start and stop, how addressing works, what ACK really is electrically, and why clock stretching can make or break your design.

START, STOP and repeated START

Animated

Data on SDA is only allowed to change while SCL is low. The two deliberate violations of that rule are the framing signals:

  • START (S): SDA falls while SCL is high — "everyone listen".
  • STOP (P): SDA rises while SCL is high — "bus is free".
  • Repeated START (Sr): a second START without an intervening STOP — keeps the bus ownership between two transfers (essential for register reads and multi-master safety).
SCL SDA S data bits (change only while SCL low) P

START: SDA falls while SCL is high. STOP: SDA rises while SCL is high. In between, SDA may only change while SCL is low.

Addressing: 7-bit (and 10-bit)

Every transfer begins with the controller broadcasting an address byte: 7 address bits plus a R/W̄ bit (1 = read, 0 = write). The one target that recognizes the address ACKs; everyone else ignores the rest of the transfer.

S
A6
A5
A4
A3
A2
A1
A0
R/W̄
ACK
Address range Reserved for
0000 000 General call (0x00) / START byte
0000 001 – 0000 111 CBUS, reserved, Hs-mode controller code
1111 0XX 10-bit addressing prefix
1111 1XX Device ID / reserved
0x08 – 0x77 Usable 7-bit device addresses (112)
Datasheet trap: some vendors quote the "8-bit address" (7-bit address already shifted left with R/W̄ = 0). If a part claims address 0x90, its 7-bit address is 0x48. When a device doesn't respond, this is the first thing to check.

10-bit addressing exists (prefix 11110XX + second address byte) but is rare in practice; support it only when a specific part needs it.

ACK / NACK — a hardware signal, not a courtesy

After every 8 bits, the transmitter releases SDA for one clock. If the receiver pulls SDA low, that's ACK; if SDA stays high (pull-up wins), that's NACK. Electrically, an ACK proves a real device sits at that address and that your pull-up, VOL and timing are all within spec — which is why a scope shot of the ACK bit is the single most useful I2C bring-up measurement (Module 07).

  • NACK on address: nobody home — wrong address, wrong bus, or device unpowered.
  • NACK on data (write): target can't accept more (buffer full, busy).
  • NACK by controller (read): deliberate — "last byte, I'm done".

Clock stretching

A slow target can hold SCL low after an ACK until it's ready — the controller must detect that SCL hasn't actually risen and wait. That's only possible because SCL is open-drain too.

Hardware checklist implications: (1) verify your controller's I2C peripheral supports clock stretching — bit-banged and some low-end implementations don't; (2) if a target datasheet mentions stretching (many EEPROMs, SMBus devices, sensor hubs), never drive SCL push-pull; (3) a stuck stretch looks exactly like a hung bus — set a timeout in firmware.

The three transactions you'll actually use

1. Plain write — set a register, send a command:

S
ADDR+W
A
DATA
A
DATA
A
P

2. Plain read — read from the target's current position:

S
ADDR+R
A
DATA
A
DATA
N̄
P

3. Register read (write-then-read) — the pattern 95 % of sensor traffic uses. Note the repeated START: the bus is never released between pointing at the register and reading it.

S
ADDR+W
A
REG
A
Sr
ADDR+R
A
DATA
N̄
P

Key takeaways

  • START/STOP are SDA transitions while SCL is high; everything else changes only while SCL is low.
  • 112 usable 7-bit addresses; watch out for "8-bit address" datasheets.
  • ACK is electrical proof your bus works; the ACK bit is your best scope target.
  • Support clock stretching in the controller, and set a firmware timeout for it.
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