FREE DEMO

Signal Integrity in 5 Minutes

Every high-speed PCB trace is a transmission line. Every via is a discontinuity. Every routing decision impacts signal quality. See why SI engineering matters — and what happens when it's ignored.

10+
Interactive Modules
50+
Simulations
3
Engineering Calculators
1
Capstone Project

Why Signal Integrity Matters

At data rates above 1 Gbps, signals don't just "travel" on traces — they propagate as electromagnetic waves. Impedance mismatches cause reflections. Coupled traces generate crosstalk. Poor return paths radiate EMI. These aren't theoretical — they're the #1 cause of board re-spins.

The Problem

A DDR4 signal at 2400 MT/s has a 416ps unit interval. With rise times under 100ps, a 2-inch trace mismatch creates reflections that close the timing window. No margin = no product.

The Solution

SI simulation before and after layout predicts exactly what the silicon will see. Impedance control, termination, length matching, and stackup design eliminate re-spins.

The Outcome

First-pass success. Margins documented. Manufacturing confidence. That's what separates professional SI engineering from hope-based design.

Every Trace is a Transmission Line

When signal wavelength approaches trace length, lumped-circuit assumptions fail. The trace has characteristic impedance determined by its geometry and dielectric environment.

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Rule of Thumb: If trace length > 1/6 of the signal's rise-time distance, treat it as a transmission line. At 100ps rise time on FR4, that's just 0.3 inches.
Z0 = f(W, H, Er) — Impedance depends on trace width, height above reference plane, and dielectric constant. Change any one, and impedance changes.
v = c / sqrt(Er) — Signals travel at ~6 inches/ns on FR4 (Er=4). A 3-inch trace adds 500ps of delay.
Td = 150 ps/inch — The propagation delay for FR4 microstrip. Every inch matters in timing budgets.
Interactive Demo
Impedance Mismatch: What Reflections Look Like

The Eye Diagram: SI's Report Card

Overlay thousands of bit transitions and you get an "eye." Open eye = reliable signaling. Closed eye = bit errors. Every SI problem — reflections, crosstalk, jitter, loss — shows up in the eye.

Interactive Demo
DDR4 Eye Diagram — Adjust Channel Loss
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What to look for: Eye height (voltage margin), eye width (timing margin), jitter (horizontal scatter), and noise (vertical thickness). In the full training, you'll learn to measure all of these and predict BER.

Interactive: Plane Split PCB Viewer

A ground plane split forces return current to detour around the gap, creating a large current loop. This radiates EMI and couples noise to adjacent traces. See how split width and signal frequency affect the problem.

Interactive Demo
PCB Cross-Section & Return Current Path
Loop Area: — EMI Risk: — Coupling: —
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Design Rule: Never route high-speed signals over plane splits or slot discontinuities. If a power-domain boundary is unavoidable, use stitching capacitors (100nF–1nF) placed within 50 mil of the signal crossing point to provide a return current path.

What the Full Training Covers

Transmission Lines

Impedance, propagation, reflections, TDR analysis, lossy vs lossless models

Impedance Matching

Series/parallel termination, ODT, reflection diagrams, lattice analysis

Crosstalk

NEXT, FEXT, coupling mechanisms, 3H rule, guard traces, ground shielding

Return Paths

Current return flow, plane splits, via transitions, stitching capacitors

Power Integrity

PDN impedance, target impedance, decoupling, anti-resonance

Differential Signaling

Zdiff, coupling, mode conversion, skew, USB/PCIe/HDMI standards

High-Speed Interfaces

DDR4/5, PCIe Gen3-6, USB4, Ethernet, loss budgets, channel compliance

Eye Diagrams

PRBS patterns, jitter decomposition, BER estimation, mask testing

SI Simulation

IBIS models, S-parameters, pre/post-layout workflow, equalization

DDR4 Capstone

Full industry-style SI verification project — 11 phases from requirements to engineering sign-off

Ready to Master Signal Integrity?

10 interactive modules. Real engineering tools. Hands-on simulations. No prerequisites — just curiosity and a browser.

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Free access to all modules, calculators, and the DDR4 capstone project.