Impedance Matching & Signal Reflection Control
Master termination strategies, bounce diagrams, and practical impedance matching techniques for high-speed PCB design.
Course Overview
Impedance mismatches are the root cause of signal reflections — the single most common signal integrity failure mode in high-speed PCB design. Every time a signal encounters a change in impedance — at a connector, via, stub, or unterminated receiver — energy reflects back along the transmission line, creating overshoot, undershoot, ringing, and potentially false switching.
This module teaches you to identify, analyze, and eliminate reflections through proper termination design. You will master source termination, end termination, AC termination, and Thevenin networks — understanding not just how they work, but when and why to choose each approach for specific interface requirements.
Learning Objectives
After completing this module, you will be able to:
Introduction to Signal Reflections
Why Do Reflections Occur?
When a signal's rise time becomes comparable to the propagation delay of a PCB trace, the trace behaves as a transmission line rather than a simple wire. The signal travels as an electromagnetic wave — and just like light hitting a boundary between two materials, an electrical wave encountering an impedance discontinuity splits into a transmitted portion and a reflected portion.
Reflections occur at every point where impedance changes: at the driver output, connectors, vias, trace width changes, and the receiver input. The amount of energy reflected is determined by the ratio of impedance mismatch — quantified by the reflection coefficient Γ.
The Reflection Process
Driver outputs a voltage step. Initial voltage divides between ZS and Z0.
Wave travels along the trace at vp. No reflection on uniform line.
At load: ΓL of incident energy reflects. Remainder enters the load.
Reflected wave bounces between source and load, creating ringing until energy dissipates.
Reflection Formation Visualizer
Watch a signal launch from the driver, propagate along the trace, and generate reflections at the mismatched load. The oscilloscope updates in real-time showing voltage at driver and receiver.
Reflection Coefficient Fundamentals
The Reflection Coefficient (Γ)
The reflection coefficient quantifies how much of an incident wave reflects at an impedance boundary. It is defined as the ratio of reflected voltage to incident voltage and depends only on the impedance seen by the wave at the discontinuity.
Physical Meaning of Γ
Source Reflection Coefficient: When a reflected wave returns to the driver, it encounters the source impedance and reflects again. ΓS = (ZS − Z0) / (ZS + Z0). For low-impedance CMOS drivers (ZS ≈ 10Ω), ΓS ≈ −0.67, causing further bouncing that decays over multiple round trips.
Reflection Coefficient Calculator
Calculate Γ for Common Scenarios
Work through each case mentally before revealing the solution.
50Ω trace → 50Ω load
50Ω trace → Open (ZL=∞)
50Ω trace → Short (ZL=0)
50Ω trace → 100Ω load
Γ = 0 / 100
Γ = 0.000 — No reflection!
Γ = ∞ / ∞
Γ = +1.000 — Total positive reflection
Γ = −50 / 50
Γ = −1.000 — Total negative reflection
Γ = 50 / 150
Γ = +0.333 — 33% reflected voltage
Source Termination
Series Termination at the Source
Source termination places a series resistor between the driver and the transmission line. The goal is to make the total source impedance equal to the trace characteristic impedance:
When the driver impedance plus the series resistor matches Z0, the source reflection coefficient becomes zero (ΓS = 0). Any reflection returning from the load is completely absorbed at the source — no secondary reflections occur. The receiver initially sees a half-amplitude step (voltage divider: Rseries + Zdriver and Z0), which doubles to full amplitude after the first round-trip.
- ✓ Lowest power consumption (no DC current path)
- ✓ Minimal components (single resistor)
- ✓ Ideal for point-to-point interfaces
- ✓ No static power draw when line is high or low
- ✗ Receiver sees half-voltage for one propagation delay
- ✗ Not suitable for multi-drop (bus) configurations
- ✗ Adds slight propagation delay
- ✗ Driver output impedance varies with process/voltage
Source Termination: Before vs After
Compare signal integrity with and without source termination. Adjust driver impedance and termination resistor to observe how reflections are suppressed.
Source Termination Calculator
End Termination (Parallel Termination)
Parallel Termination at the Receiver
End termination (also called parallel termination) places a resistor at the receiver end of the transmission line, connected to ground (or a reference voltage). When the termination resistance equals the trace characteristic impedance, the reflection coefficient at the load becomes zero:
Unlike source termination where the receiver sees a half-amplitude step initially, end termination delivers full signal amplitude immediately at the receiver on the first arrival. This makes it ideal for timing-critical interfaces. However, the termination resistor creates a constant DC current path whenever the line is driven, resulting in significantly higher power consumption.
- ✓ Full amplitude at receiver on first arrival
- ✓ Zero reflection — completely clean waveform
- ✓ Works for multi-drop bus configurations
- ✓ No timing penalty from voltage build-up
- ✗ High static power dissipation (DC current)
- ✗ Driver must source current continuously
- ✗ Reduces voltage swing due to resistive loading
- ✗ Requires stronger driver capability
Waveform Comparison: Without vs With End Termination
Compare receiver-end waveforms with and without parallel termination. Observe how a matched load eliminates reflections and delivers a clean first-incident wave.
Power Dissipation Calculator
AC Termination
Series RC Network Termination
AC termination uses a series RC network at the receiver to provide frequency-dependent termination. The capacitor blocks DC current while the resistor absorbs high-frequency signal energy. This achieves effective termination for clock and periodic signals while dramatically reducing static power consumption.
At high frequencies (where signal transitions occur), the capacitor's impedance is low, making the RC network look like a resistance to ground — providing effective termination. At DC, the capacitor blocks current entirely, eliminating static power draw. The cutoff frequency of the RC network determines the boundary between effective and ineffective termination:
- ✓ Near-zero static power consumption
- ✓ Effective termination at signal frequencies
- ✓ Excellent for clock signals and periodic waveforms
- ✓ Full voltage swing (no DC voltage divider)
- ✗ Frequency dependent — requires tuning
- ✗ Ineffective for low-frequency or random data
- ✗ Capacitor adds board space (2 components)
- ✗ RC time constant must match signal bandwidth
AC Termination Frequency Response
Thevenin Termination
Dual-Resistor Voltage Divider Termination
Thevenin termination uses two resistors in a voltage divider configuration to create both an equivalent termination impedance and a DC bias voltage at the receiver. The parallel combination of R1 and R2 must equal the trace characteristic impedance, while the voltage divider sets the receiver's idle bias point.
Thevenin termination provides excellent reflection absorption (equivalent to parallel termination) while also establishing a known DC bias level. This is particularly useful for buses that need a defined idle state (e.g., I²C pull-ups, multi-drop buses). The trade-off is moderate power consumption — less than parallel-to-ground but more than source termination.
Thevenin Termination Calculator
Thevenin vs Other Termination Methods
Compare Thevenin (split resistor) termination against parallel and no-termination scenarios. Adjust the divider ratio to see how bias voltage and signal integrity change.
Comparative Termination Study
Termination Method Comparison Dashboard
Source (Series) Termination
Series resistor at driver output. Eliminates secondary reflections by matching total source impedance to Z0. Receiver sees half-swing for one propagation delay before settling to full value.
- • Point-to-point DDR address/command
- • SPI clock/data lines
- • FPGA I/O (short traces)
- • Low-power interfaces
Parallel (End) Termination
Resistor to ground at receiver. Absorbs all incident energy immediately — zero reflection, full amplitude on first arrival. Highest power but best signal quality.
- • High-speed clock distribution
- • CML/PECL interfaces
- • RF and microwave signals
- • Ethernet PHY interfaces
AC (Series RC) Termination
Series RC to ground at receiver. Capacitor blocks DC for zero static power. Effective at signal frequencies above the RC cutoff. Best for periodic signals (clocks).
- • Clock signal termination
- • Periodic data buses
- • Low-power high-speed links
- • Battery-powered systems
Thevenin (Voltage Divider) Termination
Two-resistor divider provides both termination impedance and DC bias. Excellent for multi-drop buses and interfaces requiring defined idle voltage levels.
- • I²C bus termination
- • CAN bus networks
- • Multi-drop address buses
- • SCSI termination (legacy)
Comparison Matrix
| Parameter | Source | Parallel | AC | Thevenin |
|---|---|---|---|---|
| Power Consumption | Very Low | High | Low | Medium |
| Component Cost | Low | Low | Medium | Medium |
| Reflection Control | Good | Excellent | Good | Excellent |
| High-Speed Capability | Good | Excellent | Excellent | Excellent |
| Multi-Drop Bus | Poor | Good | Good | Good |
| PCB Area Required | Minimal | Small | Medium | Medium |
| Ease of Implementation | Easy | Easy | Moderate | Moderate |
Reflection Visualization Laboratory
Transmission Line Reflection Simulator
Full transmission line simulator with selectable termination strategies. Compare before/after waveforms and observe how each method controls reflections.
Reflection Coefficient vs Load Impedance
Real PCB Design Case Studies
Why: Point-to-point topology, low power budget for 64+ address lines, receiver settles within setup time window.
Why: Simple, one resistor per signal, eliminates ringing at slave without power penalty. MISO from slave may not need termination if trace is short.
Why: Periodic signal makes AC termination effective. Saves power vs parallel while maintaining clean edges for timing margin.
Why: LVDS standard mandates 100Ω differential termination. Constant-current driver means power is already fixed. Clean signal required at multi-Gbps.
Module 3 Quiz
20 questions covering reflection calculations, waveform interpretation, and termination selection.
- Γ = 0
- Γ = +0.5
- Γ = +1
- Γ = −1
- High clock frequency
- Long trace length
- Impedance discontinuity
- High current draw
- Γ = 0
- Γ = −1
- Γ = +0.5
- Γ ≈ +1
- Absorbing reflections at the load end
- Making source impedance equal Z0 so returning reflections are absorbed
- Filtering out high-frequency components
- Reducing the signal rise time
- 3.3V
- 1.65V
- 2.75V
- 0.55V
- The termination resistor conducts DC current in the steady state
- It increases trace capacitance
- It reduces signal amplitude
- It increases source impedance
- Random data patterns with long idle periods
- DC level shifting
- Periodic clock signals where DC power savings are critical
- Traces shorter than 1 inch
- Zero DC power consumption
- A defined DC bias voltage at the termination point plus impedance matching
- Source impedance matching only
- Frequency-selective termination
- Source (series) termination
- End (parallel) termination
- Thevenin termination
- No termination needed
- 2.75V
- 3.3V
- 1.65V
- 5.5V (voltage doubling)
- 50 Ω
- 35 Ω
- 15 Ω
- 65 Ω
- Source termination only
- End termination at the far end of the bus
- No termination — multi-drop is inherently matched
- Capacitive termination at each receiver
- 0.5 ns
- 1.0 ns
- 2.0 ns
- 6.0 ns
- High DC power consumption
- Requires two resistors per signal
- Intermediate receivers see half-amplitude signal during propagation
- Only works for differential signals
- 30%
- 3%
- 9%
- 15%
- Impedance mismatch with positive ΓL and reflection bouncing
- Crosstalk from adjacent traces
- Power supply noise coupling
- Excessive trace capacitance
- R1 = 50Ω, R2 = 50Ω
- R1 = 100Ω, R2 = 100Ω
- R1 = 75Ω, R2 = 150Ω
- R1 = 200Ω, R2 = 200Ω
- 15.9 MHz
- 31.8 MHz
- 100 MHz
- 318 MHz
- Doubles in amplitude (same polarity)
- Is completely absorbed
- Inverts (negative reflection, Γ = −1)
- Continues without reflection
- The frequency is above 50 MHz
- The trace is longer than 6 inches
- The signal amplitude exceeds 2V
- The signal rise time is shorter than the round-trip delay
Final Design Challenge: FPGA Clock Interface
A 3.3V FPGA drives a 100 MHz reference clock across a 12-inch FR4 PCB trace to a remote clock buffer IC. The FPGA I/O bank has a measured output impedance of 15Ω. The trace is routed as a 50Ω controlled-impedance microstrip. The receiver is a standard CMOS input (high-Z).
ΓS = (15−50)/(15+50) = −35/65 = −0.538
Nearly total reflection at the receiver. Multiple bounce ringing will occur.
Reasoning: Point-to-point topology (single driver → single receiver), low power requirement, periodic clock signal. Source termination provides excellent reflection control with minimal power. Alternative: AC termination (50Ω + 100pF) for zero static power if the clock is always running.
Nearest standard value: 33Ω (E24 series). This gives total source Z = 48Ω, ΓS = −0.02 (negligible).
AC Termination alternative: R = 50Ω, C = 100pF (fcutoff = 31.8 MHz, well below 100 MHz signal).
Dynamic: Pdyn = Cload × V2 × f ≈ negligible additional from resistor itself.
Comparison — if parallel termination: P = V²/R = 3.3²/50 = 218 mW (DC current always flowing).
Source termination saves ~218 mW per line — critical for multi-output FPGA banks.
After (33Ω source term): Initial step to ~1.65V at receiver, doubles to 3.3V after one round-trip (3.6ns), no secondary reflection. Clean monotonic settling, zero ringing. Meets all SI specs.
✓ Overshoot < 10% of VCC: PASS (0% with source term)
✓ Undershoot < −0.3V: PASS (no undershoot)
✓ Settling time < Tperiod/2 (5ns): PASS (settles in 3.6ns)
✓ Monotonic edge: PASS (single step-up)
✓ Power budget: PASS (0 mW static)
✓ VIH threshold met: PASS (3.3V > 2.0V threshold)
DESIGN APPROVED — All signal integrity requirements satisfied.
Trace: 50Ω microstrip, 12 inches, FR4
Tpd = 1.8ns (one-way), RT = 3.6ns
Receiver: CMOS buffer, ZL > 1MΩ
Signal: 100 MHz clock, tr ≈ 0.5ns
Rseries = 33Ω (standard E24 value)
Total Zsource = 48Ω (ΓS ≈ −0.02)
Static Power: 0 mW
Component Count: 1 (per signal)