Fundamentals of Signal Integrity
Understand what Signal Integrity is, why it matters at high speeds, and how to identify signal quality problems.
Course Overview
This module introduces the foundational concepts of Signal Integrity (SI) — the discipline that ensures electrical signals arrive at their destination with sufficient quality, timing, and voltage levels to be correctly interpreted. As modern digital systems push beyond multi-gigabit data rates, understanding SI is no longer optional — it is essential for every engineer involved in PCB design, hardware development, and embedded systems.
You will explore why a signal that passes logic thresholds can still have integrity problems, how increasing edge rates transform simple wires into complex transmission lines, and how common phenomena like overshoot, undershoot, ringing, and noise degrade system reliability. Through interactive simulations, waveform visualizations, and engineering exercises, you will develop the intuition needed to identify and prevent SI issues in real-world designs.
Learning Objectives
Upon successful completion of this module, you will be able to demonstrate the following competencies. Each objective is mapped to a specific section and assessment question.
Each objective is assessed through the 15-question knowledge check quiz (Q1–Q15) and the capstone design exercise. A passing score of 80% (12/15 correct) is required to mark this module as complete. The design exercise is self-assessed with a guided solution.
Introduction to Signal Integrity
What is Signal Integrity?
Signal Integrity (SI) is the measure of an electrical signal's ability to propagate through an interconnect and arrive at the receiver with sufficient quality — correct voltage levels, clean transitions, proper timing, and minimal distortion — to be reliably interpreted. It encompasses every phenomenon that degrades a signal between transmitter and receiver: reflections, crosstalk, attenuation, noise coupling, and timing skew.
SI is not simply about whether a signal "works." A digital signal may cross logic thresholds and appear functional in lab testing, yet harbor marginal integrity that causes intermittent failures in production, at temperature extremes, or across component lot variations. The discipline of Signal Integrity quantifies these margins and ensures designs are robust across all operating conditions.
Functional vs. Quality Signal Transmission
The signal crosses the receiver's input threshold voltages (VIH and VIL) and the device registers correct logic states. The system appears to work.
- • Passes basic functional test
- • Logic levels recognized
- • May have hidden margin issues
- • Susceptible to environmental variation
The signal arrives with controlled overshoot, monotonic edges, adequate noise margin, proper timing, and predictable behavior across voltage/temperature corners.
- • Verified margin at all corners
- • Clean, monotonic transitions
- • Minimal overshoot/undershoot
- • Robust across production variation
Key Insight: A signal that passes logic thresholds today may fail tomorrow. Temperature drift, component aging, voltage supply variation, and production lot differences all erode noise margins. SI engineering ensures the signal remains valid across the entire operating envelope — not just nominal bench conditions.
Signal Quality and System Reliability
Every digital system has a target Bit Error Rate (BER). For high-speed serial links like PCIe Gen5, the required BER is 10-12 — meaning fewer than one error per trillion bits. Achieving this requires signal quality far beyond simple threshold crossing. The relationship between signal quality and reliability is exponential: small degradations in signal margin cause disproportionately large increases in error rate.
Real-World SI Applications
Signal Integrity challenges are present in virtually every modern electronic interface. The following examples illustrate how SI constraints drive design decisions across different protocols:
Parallel bus running at 3200–6400 MT/s. Requires precise length matching (±5 mils within byte lanes), controlled impedance (40Ω), fly-by topology for command/address, and on-die termination (ODT). Timing margins are <50 ps.
Differential pairs at 5–40 Gbps. Requires 85Ω differential impedance, low-loss dielectric (Dk < 3.5), AC coupling capacitors, and equalization (CTLE/DFE). Insertion loss budgets as tight as -8 dB at Nyquist.
Serial links at 16–64 GT/s using NRZ and PAM4 signaling. Demands via stub optimization, anti-pad tuning, reference plane continuity, and channel loss < 28 dB. BER target: 10-12 pre-FEC.
Requires transformer-coupled differential pairs with 100Ω impedance, strict return loss specs (< -10 dB), controlled skew within pairs (<5 ps), and compliance to IEEE 802.3 channel models.
TMDS links at 12–48 Gbps supporting 4K/8K video. Requires impedance-controlled differential routing (100Ω), length matching within 2 mils across TMDS lanes, and FRL (Fixed Rate Link) equalization.
Even "moderate" speed interfaces (SPI at 50 MHz, QSPI at 133 MHz) with sub-nanosecond edges exhibit SI issues on traces > 2 inches. Requires series termination resistors, ground plane continuity, and stub minimization.
The Water-Pipe Analogy
To build intuition, consider an electrical interconnect as a water pipe system. While imperfect, this analogy helps visualize key SI concepts before diving into electromagnetic theory:
How the analogy works: Imagine sending a sharp pressure pulse down a long pipe. If the pipe diameter suddenly changes (analogous to an impedance discontinuity), part of the pulse energy continues forward and part bounces back as an echo. If the pipe is open-ended (no termination), the entire pulse reflects. This is exactly what happens to a voltage signal on a transmission line with an impedance mismatch.
A well-terminated pipe (matched impedance) absorbs the pulse completely with no reflection — the signal arrives cleanly. This is the goal of impedance matching in SI design.
- ✕ Water is a physical medium with mass and inertia; electrical signals are electromagnetic waves that propagate through fields, not electron movement.
- ✕ Water cannot flow backward simultaneously — but reflected EM waves superimpose on forward-traveling waves, creating standing wave patterns.
- ✕ Crosstalk (coupling between adjacent pipes) has no intuitive water analogy — EM fields extend beyond the conductor boundary.
- ✕ Frequency-dependent losses (skin effect, dielectric loss) have no water equivalent — water does not attenuate differently at different pulse speeds.
- ✕ The return path concept (ground plane) is absent in the water model — current must flow in a loop, but water can flow one-way into a reservoir.
Why Signal Integrity Matters
Historical Perspective: From Wires to Transmission Lines
The need for Signal Integrity analysis is a direct consequence of technology scaling. As silicon process nodes shrank and data rates increased, the electrical behavior of PCB interconnects fundamentally changed — transforming benign wires into complex waveguides where electromagnetic effects dominate.
Older Systems
- ● Slow edge rates: Rise times of 5–20 ns typical. Signals completed transitions smoothly with minimal high-frequency content.
- ● Low frequencies: Clock rates under 100 MHz. Wavelengths far longer than any trace on the board.
- ● Short interconnects: Most traces under 3 inches. Propagation delay insignificant compared to edge rate.
- ● Result: Traces behaved as ideal wires. No impedance control or termination needed. SI was not a concern.
Modern Systems
- ● Fast rise times: Edge rates of 30–500 ps. Signal transitions contain frequency content exceeding 7 GHz.
- ● Multi-gigabit links: Data rates of 5–112 Gbps per lane. NRZ, PAM4, and PAM8 modulation schemes.
- ● Dense PCBs: 12–20 layer stackups with thousands of high-speed nets routed in tight proximity.
- ● Long routing channels: Backplane traces exceeding 20 inches. Connector-via-trace-via-connector chains.
Edge Rate Matters More Than Clock Frequency
A common misconception is that only high-frequency clocks cause SI problems. In reality, it is the edge rate (rise/fall time) — not the repetition rate — that determines whether a trace behaves as a transmission line. A 50 MHz clock with a 500 ps rise time contains far more high-frequency energy than a 50 MHz clock with a 10 ns rise time.
Result: Although the clock repeats at only 50 MHz, the signal's frequency content extends to 700 MHz. This means the trace must be treated as a transmission line if its propagation delay approaches or exceeds tr/6 ≈ 83 ps — equivalent to only ~0.5 inches on FR4. A "50 MHz" signal needs high-speed design practices.
Critical Length ≈ tr / 6 × vp (where vp ≈ 6 in/ns on FR4)
Slow Edge vs. Fast Edge — Animated Comparison
Watch how edge rate affects signal quality at the receiver. The slow edge arrives with minimal distortion; the fast edge exhibits reflections due to impedance discontinuities along the trace.
- • Gentle waveform transition (5 ns)
- • Signal settles within one transition
- • No reflections visible
- • Minimal high-frequency content
- • BW ≈ 0.35 / 5 ns = 70 MHz
- • Sharp transition (300 ps)
- • Overshoot exceeds VCC
- • Multiple reflections (ringing)
- • Significant high-frequency energy
- • BW ≈ 0.35 / 300 ps = 1.17 GHz
The Consequences of Ignoring SI
As edge rates decrease below 1 ns, even short PCB traces exhibit transmission line behavior. A signal traveling at ~6 inches/ns on FR4 means a 3-inch trace has 500 ps of propagation delay — comparable to the signal's rise time. When the propagation delay exceeds roughly 1/6 of the rise time, transmission line effects become significant and impedance matching is required.
Digital Signal Quality
The Ideal Digital Signal
In textbooks and simulation models, digital signals are represented as perfect square waves — instantaneous transitions between two clean voltage levels. This mathematical abstraction is useful for logic design but does not exist in the physical world.
- ● Instant rise: Transition from LOW to HIGH in zero time (tr = 0)
- ● Instant fall: Transition from HIGH to LOW in zero time (tf = 0)
- ● Perfect logic levels: Exactly VCC for HIGH and 0V for LOW — no intermediate values
- ● No distortion: Flat tops, no ringing, no noise, no droop — pure rectangular waveform
- ✕ Infinite bandwidth required: A perfect square wave contains infinite harmonics (per Fourier theory). No physical system has infinite bandwidth.
- ✕ Parasitic capacitance: Every node has capacitance to ground and adjacent traces. Charging/discharging capacitance takes finite time.
- ✕ Finite driver current: Output drivers have limited sourcing/sinking capability — slew rate is bounded by I = C × dV/dt.
- ✕ Transmission line effects: Signal propagation is governed by LC distributed elements, imposing finite velocity and reflections.
The Real Digital Signal
In practice, every digital signal exhibits non-ideal behavior. Understanding these imperfections — and quantifying them — is the core skill of Signal Integrity engineering.
Visual Comparison: Ideal vs. Real Waveform
Compare the mathematically ideal signal (left) with a physically realistic signal (right). Key parameters are annotated on the real waveform.
- • Rise time = 0 (instantaneous)
- • Fall time = 0 (instantaneous)
- • VOH = exactly 3.3V
- • VOL = exactly 0V
- • No ringing, no noise, no delay
- • Rise Time (tr): 10%–90% transition time
- • Fall Time (tf): 90%–10% transition time
- • Propagation Delay (tpd): Driver → Receiver
- • Noise Margin: VOH - VIH (high) / VIL - VOL (low)
- • Overshoot / Ringing visible on edges
Common Signal Integrity Problems
When signals travel along PCB traces at high speeds, the interconnect behaves as a transmission line — and any impedance discontinuity, mismatch, or coupling path introduces distortion. Below are the four most common SI problems, each with animated waveform demonstrations showing exactly what to look for on an oscilloscope.
4.1 Overshoot
Definition: Overshoot occurs when a signal transiently exceeds its intended high logic level (VOH) during a low-to-high transition.
Causes:
- Source impedance lower than trace impedance (under-terminated)
- Inductive parasitics in IC package leads
- Reflections from open-ended (unterminated) receiver
- Excessive driver strength for the load
Impact: Overshoot can forward-bias ESD protection diodes to VDD, injecting current into the supply rail. Repeated stress causes oxide degradation, latch-up, or immediate device failure. Even sub-destructive overshoot shrinks VIH noise margin at the receiver.
4.2 Undershoot
Definition: Undershoot occurs when a signal transiently drops below its intended low logic level (VOL) — often below ground (0V) — during a high-to-low transition.
Causes:
- Impedance mismatch on falling edge (same mechanism as overshoot)
- Ground bounce from simultaneous switching (SSN/SSO)
- Insufficient bypass capacitance near driver
- Long return path loops creating inductive drop
Damage Mechanisms: Below-ground undershoot forward-biases substrate diodes, injecting minority carriers that can trigger latch-up. In CMOS, currents as low as 100mA can destroy the device. Even without latch-up, substrate injection causes logic upset in adjacent gates.
4.3 Ringing
Mechanism: Ringing is the oscillatory behavior caused by multiple reflections bouncing between the driver and receiver ends of a transmission line. Each reflection inverts and attenuates, creating a decaying oscillation.
Transmission Line Effect: When the trace propagation delay exceeds approximately 1/6 of the rise time (tpd > tr/6), the trace acts as a transmission line. Any impedance discontinuity — via, connector, stub, plane split — generates a reflection.
Reflection Coefficient:
Open end: Γ = +1 (full positive reflection). Short end: Γ = -1 (full negative reflection). Matched load: Γ = 0 (no reflection — ideal).
4.4 Noise
Noise is any unwanted voltage or current superimposed on the signal. Unlike overshoot and ringing (which are deterministic), noise sources can be both deterministic and random.
Generated by thermal agitation of charge carriers. Broadband, Gaussian distributed. Cannot be eliminated — only minimized by reducing bandwidth or lowering temperature.
Simultaneous switching of multiple outputs (SSO) causes L·(dI/dt) voltage drops across shared power/ground pins. Creates false logic transitions on quiet nets sharing the same power domain.
Electromagnetic coupling between adjacent traces via mutual capacitance (Cm) and mutual inductance (Lm). NEXT appears at driver end; FEXT appears at receiver end. Increases with coupling length and decreases with spacing.
Transient voltage differential between the IC's internal ground and the PCB reference plane, caused by package lead inductance during high-current switching events. Solved with low-inductance packages (BGA) and distributed decoupling.
Visual Summary: Good Signal vs. Bad Signal
- Clean, sharp edges
- Stable logic levels
- No ringing or overshoot
- Full noise margin preserved
- Overshoot exceeds VOH
- Undershoot dips below GND
- Ringing takes multiple cycles to settle
- Noise margin consumed — false triggering likely
Key Insight: A signal can pass logic thresholds (register as 0 or 1) and still have severe SI problems. The receiver may see the correct logic state this time, but the reduced noise margin means the next switching event — under slightly different temperature, voltage, or process conditions — may produce a bit error. SI is about margin, not just functionality.
Understanding Edge Rates
Why Edge Rate Matters More Than Clock Frequency
The frequency content of a digital signal is not determined by its repetition rate (clock frequency) — it is determined by the speed of its transitions. A sharp edge contains energy at frequencies far higher than the fundamental clock frequency. This is because the Fourier series of a trapezoidal pulse includes harmonics whose amplitude falls off based on the edge rate, not the period.
The practical bandwidth — the highest frequency at which significant energy exists — is determined by the empirical approximation known as the "knee frequency":
A digital signal with finite rise/fall time has a frequency spectrum that rolls off in two stages:
- • Below f = 1/(π × tperiod): Amplitude is flat (determined by pulse amplitude)
- • Between 1/(π × tperiod) and 1/(π × trise): Amplitude rolls off at -20 dB/decade
- • Above 1/(π × trise) (the knee frequency): Amplitude rolls off at -40 dB/decade
Harmonics above the knee frequency have negligible energy and can be ignored for SI analysis — but those below it must be preserved by the channel.
Interactive Edge Rate Demonstration
Adjust the rise time slider to observe how the waveform shape, frequency spectrum, and signal quality indicators change in real time.
Interactive Waveform Simulator
Oscilloscope-Style Signal Analyzer
Adjust the sliders to see how rise time, noise, and load capacitance affect signal quality. The ideal signal (cyan) is overlaid with the distorted signal (orange). Real-time metrics update instantly as you explore parameter space.
Why Signal Integrity Matters
As edge rates decrease below 1 ns, even short PCB traces exhibit transmission line behavior. A signal traveling at ~6 inches/ns on FR4 means a 3-inch trace has 500 ps of propagation delay — comparable to the signal's rise time. When the propagation delay exceeds roughly 1/6 of the rise time, transmission line effects become significant and impedance matching is required.
Engineering Design Implications
How Poor Signal Integrity Impacts Product Success
Signal Integrity failures manifest in ways that are often misdiagnosed as firmware bugs, power supply issues, or component defects. Understanding the downstream consequences of poor SI helps justify the time and cost of proper high-speed design practices.
When noise margin is insufficient, the receiver samples incorrect logic states. This causes bit errors that may appear as corrupted data, CRC failures, link retraining, or silent data corruption in memory systems.
- • Random bit flips in DDR memory reads
- • USB packet CRC errors under load
- • Intermittent link drops on PCIe buses
- • ECC corrections masking underlying SI problems
Overshoot and ringing create high-frequency spectral content that radiates from PCB traces acting as antennas. This causes the product to fail FCC/CE emissions testing — often discovered late in the design cycle at significant cost.
- • Harmonics from fast edges exceed emissions limits
- • Return path discontinuities create slot antennas
- • Common-mode currents from imbalanced differential pairs
- • Ringing frequencies land in regulated bands
Marginal SI designs may pass lab testing but fail in production due to component lot variation, temperature extremes, or voltage droop under load. These "no-trouble-found" returns are expensive and damage brand reputation.
- • Works at 25°C, fails at 85°C (timing margin gone)
- • Passes with vendor A parts, fails with vendor B
- • Intermittent crashes under heavy I/O load
- • Increased failure rate after 12–18 months (degradation)
Industry standards (USB-IF, PCI-SIG, JEDEC) define strict electrical masks for eye diagrams, jitter, and voltage levels. Products must pass compliance testing to carry certification logos and be interoperable.
- • USB eye diagram fails at connector due to via stubs
- • PCIe receiver jitter tolerance violated
- • DDR write-leveling fails due to flight-time skew
- • HDMI CTS fails on inter-pair skew specification
Overshoot exceeding absolute maximum ratings causes cumulative gate oxide damage, hot-carrier injection, and latch-up in CMOS inputs. The device may work initially but degrade over months or years.
- • Gate oxide breakdown from sustained overshoot > VCC + 0.5V
- • Latch-up from undershoot below GND - 0.7V
- • Electromigration from high-frequency current concentration
- • ESD protection clamp fatigue from repeated triggering
Real-World Design Examples
The following examples illustrate how SI problems appear in specific design contexts and the engineering decisions required to mitigate them:
DDR4/DDR5 Memory Systems
DDR memory operates with timing margins measured in picoseconds. A DDR4-3200 interface has a unit interval of only 312 ps, with a valid data window that may be as small as 50 ps after accounting for jitter, skew, and ISI. Every routing decision directly impacts whether the memory link achieves its target speed.
- ✕ Byte-lane length mismatch causes DQS-to-DQ skew failures
- ✕ Impedance mismatch on fly-by topology creates reflections on CMD/ADDR
- ✕ Inadequate power delivery causes VREF noise that shifts thresholds
- ✕ Via stubs on BGA breakout add capacitive loading
USB 3.2 / USB4 Interfaces
USB SuperSpeed operates at 5–20 Gbps (USB 3.2) and up to 40 Gbps (USB4) using differential signaling. The channel must maintain 85Ω differential impedance through connectors, cables, and PCB routing while keeping insertion loss within the link budget.
- ✕ Impedance discontinuity at Type-C connector pad causes return loss failure
- ✕ Excessive via stub length on breakout creates notch in insertion loss
- ✕ Intra-pair skew from unequal trace lengths closes the eye
- ✕ High-Dk substrate causes excessive channel loss at Nyquist
FPGA Designs (Xilinx/Intel)
Modern FPGAs integrate hundreds of multi-gigabit transceivers (GTH/GTY at 16–32 Gbps) alongside thousands of GPIO pins with configurable drive strength and slew rate. The PCB must support both the high-speed serial links and the parallel I/O banks simultaneously.
- ✕ SSO (simultaneous switching output) noise on I/O banks corrupts adjacent signals
- ✕ Power plane resonance from BGA breakout via field
- ✕ MGT channel loss exceeds FPGA receiver equalization capability
- ✕ Crosstalk between dense LVDS pairs in I/O banks
High-Speed Processor Designs
Modern processors (Intel/AMD/ARM) communicate with chipsets, memory, and peripherals over dozens of high-speed serial and parallel links simultaneously. The PCB must deliver power to >200A load while maintaining sub-milliohm impedance across GHz frequencies.
- ✕ PCIe Gen5 link fails training due to channel loss exceeding PHY equalization range
- ✕ Power delivery network resonance creates supply noise that modulates signal thresholds
- ✕ BGA escape routing under processor socket creates impedance discontinuities
- ✕ Thermal-induced dielectric constant shift changes trace impedance at operating temperature
The Cost of Getting SI Wrong
Investing in SI analysis before layout costs 10–100x less than fixing problems after fabrication. Simulation catches issues when changes are free — on-screen, not on-silicon.
Practical PCB Examples
Good Routing vs. Bad Routing
The following annotated diagrams illustrate the PCB layout practices that preserve signal integrity versus common routing mistakes that degrade it. These visual patterns are the most frequent SI-related issues found during design reviews.
- ✓ Trace width calculated for target Z₀ based on stackup geometry
- ✓ Consistent width maintained throughout entire route
- ✓ Impedance verified with 2D field solver (±10% tolerance)
- ✓ Stackup designed with SI requirements driving layer assignment
- ✓ Unbroken reference plane directly below/above signal trace
- ✓ Return current follows signal path (image current)
- ✓ Stitching vias placed at every layer transition
- ✓ Minimal current loop area reduces inductance and EMI
- ✓ Series termination (Rs) placed within 200 mils of driver
- ✓ Rs value = Z₀ - Rout (matches source impedance to line)
- ✓ Eliminates reflections at the source for point-to-point links
- ✓ Alternative: parallel termination at receiver for bus topologies
- ✕ T-junction creates unterminated branch that reflects energy
- ✕ Via stubs (unused barrel below signal layer) cause notch in frequency response
- ✕ Resonance frequency: fnotch = c / (4 × stub length)
- ✓ Fix: Back-drill vias or use blind/buried vias to eliminate stubs
- ✕ Signal crosses gap in reference plane — return current must detour
- ✕ Increased loop area creates EMI and susceptibility problems
- ✕ Impedance changes abruptly at split boundary → reflections
- ✓ Fix: Never route high-speed signals across plane splits; use stitching caps if unavoidable
- ✕ Signal routed on Layer 1, reference plane on distant Layer 8
- ✕ Huge loop area increases inductance (L ∝ area) → more ringing
- ✕ Acts as efficient antenna for both emission and susceptibility
- ✓ Fix: Route signals on layers immediately adjacent to their reference plane (L1/L2 or L3/L4)
- ✕ Signal transitions layers via a via, but no nearby ground via is placed
- ✕ Return current on L2 has no low-impedance path to L4 reference
- ✕ Creates voltage between planes → common-mode noise → EMI
- ✓ Fix: Place GND stitching via within 50 mils of every signal layer transition via
SI-Focused Design Review Checklist
Use this checklist during layout review to catch the most common SI mistakes before fabrication:
Module 1 Quiz
Select the best answer for each question. Instant feedback and detailed explanations are provided after each response.
- Ensuring the PCB has adequate copper weight for current handling
- Ensuring electrical signals arrive at receivers with sufficient quality to be correctly interpreted
- Minimizing the number of PCB layers to reduce cost
- Selecting the fastest logic family for maximum clock speed
- Yes — overshoot degrades reliability and reduces noise margin regardless of logic function
- No — if logic thresholds are met, the signal has adequate integrity
- Only if the overshoot exceeds 50% of VCC
- Only at frequencies above 1 GHz
- 100 MHz — the bandwidth equals the clock frequency
- 500 MHz — the fifth harmonic of the clock
- 1.75 GHz — calculated from BW ≈ 0.35 / tr
- 350 MHz — half the inverse of rise time
- 0% to 100% of final value
- 10% to 90% of final value
- VIL to VIH
- Ground to VCC
- Frequency content remains the same — only amplitude changes
- Bandwidth doubles from 70 MHz to 140 MHz
- Bandwidth decreases because the signal transitions more slowly
- Bandwidth increases from 70 MHz to 700 MHz — a 10x increase
- Increased power consumption in the receiver IC
- Higher electromagnetic emissions from the PCB
- Cumulative gate oxide degradation leading to eventual device failure
- Reduced clock frequency capability
- Multiple signal reflections due to impedance mismatches along the trace
- Parasitic oscillation in the driver output stage
- Power supply resonance coupling into the signal
- Thermal noise amplified by the receiver input buffer
- Parallel termination at the receiver with R = Z₀ to ground
- Series termination at the driver with Rs = Z₀ - Rout
- AC termination using a series RC network at the receiver
- Thevenin termination with two resistors to VCC and GND
- Mechanical vibration of the PCB causing intermittent contact failures
- Thermal noise in the ground plane copper
- Capacitive coupling between signal traces and the ground plane
- Voltage fluctuation on the ground rail caused by simultaneous output switching through shared inductance
- Thermal noise
- Power supply ripple
- Crosstalk
- Ground bounce
- Any rise time below 10 ns
- Rise times faster than approximately 2 ns
- Only rise times below 100 ps
- Transmission line analysis is never needed for 2-inch traces
- The return current must detour around the split, creating a large loop that increases inductance and EMI
- The split causes the trace impedance to increase to infinity
- The dielectric constant changes at the split boundary
- The split creates a short circuit between power domains
- Electromigration in the bond wires
- Dielectric breakdown of the PCB substrate
- Latch-up due to forward-biasing the substrate diode
- Increased leakage current in the power supply regulator
- -6 dB/octave
- -10 dB/decade
- -20 dB/decade
- -40 dB/decade
- Crosstalk between adjacent traces
- Overshoot exceeding absolute maximum ratings
- Ground bounce on simultaneous switching outputs
- Solder joint fatigue from thermal cycling
Capstone Problem
Scenario: Clock Signal with Integrity Issues
A microcontroller drives a 3.3V clock signal across a 10-inch PCB trace on FR4 substrate. During lab bring-up, the following waveform is captured at the receiver with an oscilloscope:
- 1. Excessive overshoot: Signal reaches 4.3V (VCC + 1.0V), exceeding the absolute maximum rating of most 3.3V CMOS devices (typically VCC + 0.5V). This is a reliability and potential latch-up risk.
- 2. Ringing: Multiple oscillations (3–4 cycles) indicate uncontrolled reflections bouncing between driver and receiver. The signal takes too long to settle, reducing the valid data window.
- 3. Transmission line effects: The 10-inch trace with 500 ps edges is electrically very long — reflections dominate the received waveform.
- 4. Reduced noise margin: Ringing around logic thresholds may cause false triggering or metastability in downstream logic.
Critical threshold: tr / 6 = 500 ps / 6 = 83 ps
Since tpd (1.67 ns) >> tr/6 (83 ps), this trace is a transmission line.
- ● Impedance mismatch at receiver: The trace is unterminated. The receiver presents a high-impedance capacitive load, causing near-total reflection (ρ ≈ +1). The reflected wave doubles the voltage at the open end.
- ● No source termination: Without series resistance at the driver, the reflected wave re-reflects off the low-impedance driver output, creating multiple round trips (ringing).
- ● Fast edge rate: BW = 0.35 / 500 ps = 700 MHz. The high-frequency content excites every discontinuity along the 10-inch path.
- ● Possible impedance discontinuities: Vias, connectors, or width changes along the 10-inch route create additional reflection points.
Rise time: tr = 500 ps = 0.5 ns
Ratio: tpd / tr = 1.67 / 0.5 = 3.33
Rule of thumb: Termination required when tpd > tr / 6
Threshold: 500 ps / 6 = 83 ps
Actual: 1670 ps >> 83 ps
VERDICT: Termination is absolutely required.
The propagation delay is 20x the critical threshold. The signal makes approximately 3.3 round trips during one rise time, creating severe ringing. Without termination, this design will:
- • Exceed absolute maximum ratings (4.3V > 3.8V max for most 3.3V CMOS)
- • Fail EMC testing due to 700 MHz spectral content radiating from the trace
- • Exhibit intermittent data errors at temperature/voltage corners
- • Degrade receiver IC reliability over the product's lifetime
Recommended fix: Add a 33Ω series resistor at the MCU output (assuming Rout ≈ 17Ω, giving 33 + 17 = 50Ω matched to Z₀). This will produce a clean half-amplitude step at the driver that doubles to full amplitude at the receiver with zero reflection. Total cost: <$0.01.
Key Takeaways
In Transmission Line Theory, you will learn the RLGC distributed model, derive characteristic impedance from first principles, understand reflection coefficients, and simulate signal propagation using lattice diagrams. These concepts build directly on the SI fundamentals covered here.