High-Speed Interface Design
Compare DDR4/DDR5, PCIe, USB, Ethernet, and MIPI interfaces — their SI requirements, impedance targets, loss budgets, and routing constraints.
DDR4 Overview
DDR4 is a parallel bus interface operating at 1.2V with data rates from 1600 to 3200 MT/s. It uses source-synchronous clocking with a fly-by topology for clock/address/command signals and point-to-point for data (DQ/DQS). The fly-by topology intentionally introduces skew between ranks, compensated by write leveling.
SI challenges include: tight impedance control (40Ω single-ended for DQ), length matching within byte lanes (<25 mil), and managing ISI at higher speeds where the eye diagram closes.
Key Specifications
| Parameter | Value |
|---|---|
| Voltage (VDDQ) | 1.2V |
| Data Rate | 1600–3200 MT/s |
| DQ Impedance | 40Ω ±10% |
| CLK Differential | 80Ω (diff pair) |
| Topology | Fly-by (CA/CLK), P2P (DQ) |
| Max Trace Length | ~6 inches (DQ) |
| Byte-Lane Match | < 25 mil |
| Termination | ODT (on-die), 34/40/48/60Ω |
DDR5 Advances
DDR5 doubles bandwidth to 4800–8400 MT/s with 1.1V VDDQ. Key SI changes: Decision Feedback Equalization (DFE) is mandatory at the receiver, bus width splits to 2×16 (two independent 32-bit channels per DIMM), and on-DIMM VRM moves power regulation to the module.
The tighter voltage margin (1.1V with smaller swing) and doubled data rate make trace loss the dominant SI challenge. Low-loss dielectrics (Dk<3.5, Df<0.005) are often required.
DDR5 vs DDR4 Comparison
| Feature | DDR4 | DDR5 |
|---|---|---|
| Voltage | 1.2V | 1.1V |
| Max Data Rate | 3200 MT/s | 8400 MT/s |
| DQ Impedance | 40Ω | 34/40Ω |
| Channel Width | 64-bit | 2×32-bit |
| Equalization | None/DFE | DFE mandatory |
| VRM Location | Motherboard | On-DIMM (PMIC) |
| Burst Length | 8 | 16 |
PCIe Architecture
PCIe uses differential serial links with NRZ encoding (Gen 1-5) and PAM4 for Gen 6. Each lane is an independent differential pair operating at 2.5 GT/s (Gen 1) to 64 GT/s (Gen 6). Links aggregate x1 to x16 lanes. AC-coupled with 100nF blocking caps.
PCIe 5.0 (32 GT/s) requires careful attention to insertion loss (<28 dB at Nyquist), return loss (<-12 dB), and crosstalk. Low-loss materials (Megtron 6/7) become necessary above 12 inches.
PCIe Generation Comparison
| Gen | Rate | BW/Lane | Encoding |
|---|---|---|---|
| Gen 3 | 8 GT/s | ~1 GB/s | 128b/130b NRZ |
| Gen 4 | 16 GT/s | ~2 GB/s | 128b/130b NRZ |
| Gen 5 | 32 GT/s | ~4 GB/s | 128b/130b NRZ |
| Gen 6 | 64 GT/s | ~8 GB/s | PAM4 + FEC |
USB Evolution
USB has evolved from 480 Mbps (USB 2.0) to 80 Gbps (USB4 Gen 4). USB 3.x uses SuperSpeed differential pairs at 5/10/20 Gbps with 90Ω differential impedance. USB4 tunnels PCIe and DisplayPort over the same Type-C connector. Routing requires 90Ω ±10% impedance control and <15ps intra-pair skew.
USB Speed Tiers
| Standard | Speed | Zdiff | Pairs |
|---|---|---|---|
| USB 2.0 HS | 480 Mbps | 90Ω | 1 (D+/D-) |
| USB 3.2 Gen 1 | 5 Gbps | 90Ω | 1 SS |
| USB 3.2 Gen 2 | 10 Gbps | 90Ω | 1 SS |
| USB 3.2 Gen 2×2 | 20 Gbps | 90Ω | 2 SS |
| USB4 Gen 3 | 40 Gbps | 85Ω | 2 lanes |
| USB4 Gen 4 | 80 Gbps | 85Ω | 2 lanes |
High-Speed Ethernet
Ethernet PHYs use 100Ω differential pairs. 10GBASE-KR uses 10.3125 Gbaud NRZ with CTLE+DFE. 25G/50G/100G SerDes use PAM4 encoding. PCB routing: 100Ω ±10%, controlled loss (<1 dB/inch at Nyquist), AC coupling via 100nF caps.
MIPI D-PHY / C-PHY
MIPI interfaces connect cameras, displays, and sensors in mobile/automotive platforms. D-PHY uses differential pairs (200mV swing) at up to 4.5 Gbps/lane. C-PHY uses 3-wire encoding for higher efficiency (2.28 bits/symbol).
| Parameter | D-PHY | C-PHY |
|---|---|---|
| Wires/Lane | 2 (diff pair) | 3 (trio) |
| Max Speed | 4.5 Gbps | 6.0 Gsps |
| Impedance | 100Ω diff | 50Ω SE each |
| Swing | 200 mV | 250 mV |
| Max Length | ~6 inches | ~4 inches |
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