Transmission Line Theory
Master distributed parameters, characteristic impedance, wave propagation, reflections, and controlled-impedance PCB design.
Course Overview
This module explores why PCB traces cannot be treated as simple wires at high speeds, and how the distributed nature of interconnects gives rise to characteristic impedance, wave propagation, reflections, and signal degradation. You will learn to calculate impedance from physical stackup parameters, predict propagation delay, analyze reflection diagrams, and design controlled-impedance traces for modern high-speed interfaces.
Through interactive calculators, animated signal propagation visualizations, and real PCB stackup examples, you will develop the quantitative intuition needed to make impedance-aware routing decisions — the single most impactful skill in high-speed PCB design.
Learning Objectives
After completing this module, you will be able to:
Why Transmission Lines Matter
When Does a PCB Trace Become a Transmission Line?
At low speeds, a PCB trace behaves like a simple wire — the entire conductor is at the same voltage at any given instant. Current flows, voltage appears at the far end, and the trace's physical length is irrelevant. This is the lumped circuit assumption, valid when the signal's wavelength is much larger than the trace length.
As edge rates increase, the signal's electromagnetic wavefront takes finite time to travel along the trace. Different points along the conductor are at different voltages simultaneously. The trace must now be modeled as a distributed circuit — a transmission line with characteristic impedance, propagation delay, and the potential for reflections.
The transition from "wire" to "transmission line" is not a property of the trace — it is a property of the signal's rise time relative to the trace's propagation delay. A 6-inch trace is a transmission line for a 500 ps rise time signal, but a simple wire for a 50 ns rise time signal.
The Critical Length Rule
The fundamental criterion for when transmission line effects become significant:
Equivalently, the critical length is:
When the round-trip propagation delay (2 × tpd) is less than ~1/3 of the rise time, any reflection returns and settles before the signal finishes transitioning. The receiver sees a smooth edge. Beyond this threshold, the reflected wave arrives while the signal is still transitioning — creating visible distortion, overshoot, or ringing.
- LVCMOS at 50 MHz (tr = 2 ns): critical length ≈ 2 inches
- DDR4 (tr = 300 ps): critical length ≈ 0.3 inches
- PCIe Gen4 (tr = 35 ps): critical length ≈ 0.035 inches
- At PCIe Gen4+ speeds, every trace is a transmission line
Critical Length vs. Rise Time
| Signal Rise Time | BW ≈ 0.35/tr | Critical Length (FR4) | Example Interface | Action Required |
|---|---|---|---|---|
| 10 ns | 35 MHz | 10 inches | Legacy CMOS, I²C | Rarely needs TL analysis |
| 1 ns | 350 MHz | 1.0 inch | SPI >50 MHz, LPDDR3 | Impedance control needed for traces >1" |
| 500 ps | 700 MHz | 0.5 inch | DDR4, USB 2.0 HS | All signal traces need impedance control |
| 100 ps | 3.5 GHz | 0.1 inch | PCIe Gen3/4, USB 3.x | Every trace + via is a TL. Full SI simulation required. |
| 35 ps | 10 GHz | 0.035 inch | PCIe Gen5/6, 112G SerDes | Package-level TL effects. Channel simulation mandatory. |
Lumped Circuit vs. Distributed Circuit
Valid when: trace length << wavelength
- All points at same voltage simultaneously
- No propagation delay effects
- Simple R, L, C components
- Kirchhoff's laws apply directly
- No reflections possible
Required when: tpd > tr / 6
- Voltage varies along trace length
- Signal propagates as EM wave
- Characteristic impedance Z0 emerges
- Wave equations replace KVL/KCL
- Reflections at impedance discontinuities
Critical Length Calculator
Adjust the rise time to see how critical length changes. Any trace longer than Lcrit requires transmission line analysis and impedance control.
Key Insight: The same physical trace can be a "wire" for one signal and a "transmission line" for another. A 2-inch trace carrying a 10 ns rise time I²C signal is perfectly fine as a lumped element. But that same trace carrying a 300 ps DDR4 signal has a propagation delay of 333 ps — well above the 50 ps threshold (tr/6) — and must be treated as a transmission line with controlled impedance and proper termination.
Distributed Parameter Model
The RLGC Transmission Line Model
A transmission line is not a single resistor, inductor, or capacitor — it is all of these distributed continuously along its length. Every infinitesimal segment dx of the line contains four fundamental electrical parameters that arise from the physical geometry of the conductor, dielectric, and return path.
The RLGC model decomposes the transmission line into a ladder network of these per-unit-length elements. This model is the mathematical foundation for the Telegrapher's Equations — the wave equations that describe voltage and current propagation along the line.
Distributed RLGC model — each infinitesimal segment dx contains all four parameters in series and shunt configuration
The Four Distributed Parameters
Physical Origin: Finite conductivity of the copper trace. At DC, resistance is uniform across the cross-section. At higher frequencies, skin effect confines current to the outer surface, increasing effective resistance.
Typical Value: 5–50 mΩ/inch for PCB traces (frequency-dependent)
Effect: Signal attenuation (loss). Higher R means weaker signal at receiver. Dominates loss at low frequencies.
Physical Origin: Magnetic flux generated by current flowing through the trace and its return path. The loop area between signal and reference plane determines the inductance per unit length.
Typical Value: 6–10 nH/inch for microstrip on FR4
Effect: Determines impedance (Z0 = √(L/C)) and propagation velocity. Larger dielectric height = more inductance = higher impedance.
Physical Origin: Electric field between the signal trace and the reference plane, separated by dielectric material. The trace and plane form a parallel-plate capacitor (with fringing fields).
Typical Value: 2–4 pF/inch for microstrip on FR4
Effect: Determines impedance and velocity. Wider trace or thinner dielectric = more capacitance = lower impedance = slower propagation.
Physical Origin: Dielectric loss — energy dissipated as heat when the electric field polarizes the dielectric material. Characterized by the loss tangent (tanδ) of the substrate.
Typical Value: FR4 tanδ ≈ 0.02; low-loss materials (Megtron 6): tanδ ≈ 0.002
Effect: Signal attenuation at high frequencies. Dominates loss above ~1 GHz. Critical for multi-gigabit channels (PCIe Gen4+, 56G/112G SerDes).
Lossless Approximation
For initial impedance and delay calculations, we often assume R = 0 and G = 0 (lossless line). This simplification is valid for short traces at moderate frequencies where losses don't significantly attenuate the signal.
Used for impedance matching, reflection analysis, and delay calculation.
Required for channel loss analysis, eye diagram prediction, and equalization design.
Interactive Distributed Model
Adjust trace length to see how the number of distributed segments scales. Watch total R, L, C, G accumulate as the line gets longer.
Key Relationship: The characteristic impedance Z0 = √(L/C) depends only on the ratio of inductance to capacitance per unit length — not on trace length. A 1-inch trace and a 10-inch trace of identical cross-section have the same Z0. However, the total delay, total loss, and total capacitive loading all scale linearly with length.
PCB Trace Cross-Section
Microstrip vs. Stripline Geometry
The two most common transmission line structures on PCBs are microstrip (outer layer trace above a ground plane) and stripline (inner layer trace sandwiched between two reference planes). Their geometry determines impedance, velocity, and field confinement.
- Outer layer — accessible for probing and rework
- Fields partially in air, partially in dielectric
- Effective Er < bulk Er (due to fringing)
- Faster propagation than stripline
- Higher radiation / EMI susceptibility
- Inner layer — shielded between two planes
- Fields fully contained in dielectric
- Effective Er = bulk Er (no fringing to air)
- Slower propagation (higher Er)
- Lower EMI — preferred for sensitive signals
Return Current Path
Every signal requires a return path. At high frequencies, return current does not spread across the entire ground plane — it flows directly beneath the signal trace, forming the tightest possible current loop to minimize inductance. This is called the image current.
Return current takes the path of least resistance. It spreads broadly across the ground plane, following the shortest geometric path back to the source.
Return current takes the path of least inductance. It concentrates directly under the signal trace regardless of where the source is located — minimizing loop area and stored magnetic energy.
Design Rule: Never route a high-speed signal across a gap, slot, or split in its reference plane. If the return current cannot flow directly beneath the signal, it must detour — creating a large loop that increases inductance, causes impedance discontinuity, generates EMI, and degrades signal integrity. Every plane split is a potential SI disaster.
Animated Field Viewer
Adjust trace width, dielectric thickness, and reference plane spacing to see how the electric field distribution changes in real time. Field line density indicates field intensity.
Comparison: Microstrip vs. Stripline
| Parameter | Microstrip | Stripline |
|---|---|---|
| Layer Position | Outer (top/bottom) | Inner (between planes) |
| Reference Planes | One (below) | Two (above & below) |
| Effective Er | ≈ 0.6×Er + 0.4 (partial air) | = Er (fully in dielectric) |
| Propagation Velocity | Faster (≈ 6.0–6.8 in/ns) | Slower (≈ 5.4–5.8 in/ns) |
| EMI / Radiation | Higher — fields radiate | Lower — shielded by planes |
| Crosstalk | Higher (fringing fields) | Lower (contained fields) |
| Typical Use | Component connections, debug access | High-speed buses, sensitive clocks |
Characteristic Impedance
What is Characteristic Impedance?
Characteristic impedance (Z0) is the instantaneous ratio of voltage to current for a traveling wave on a transmission line. It is the impedance that an electromagnetic wave "sees" as it propagates along an infinitely long line — or equivalently, along a finite line with a perfectly matched termination.
Unlike DC resistance (which depends on trace length and copper cross-section), Z0 depends only on the cross-sectional geometry and the dielectric properties of the transmission line. A 1-inch trace and a 10-inch trace of identical cross-section have the same Z0.
DC resistance depends on trace length, width, and thickness. Z0 is independent of length — it's a wave property of the cross-sectional geometry.
Trace width, copper thickness, and distance to reference plane (dielectric height) determine the L and C per unit length.
The dielectric constant (Er) of the substrate material affects capacitance per unit length — higher Er means more C, which lowers Z0.
Standard Impedance Values & Applications
RF industry standard. PCIe, USB 3.x (SE), JTAG, SPI, general digital I/O. Compromise between loss and power handling.
Video and cable TV standard. Minimizes attenuation for long coaxial cables. HDMI, analog video, cable modem.
USB 2.0/3.x differential pairs. HDMI differential pairs. Common in consumer electronics interfaces.
Ethernet (1G/10G/25G/100G), PCIe, SATA, SAS, DDR4/5 clocks. Most common differential impedance in digital design.
Some JEDEC LPDDR standards. Occasionally used where lower power or specific driver matching is required.
Impedance Calculator
Adjust trace parameters and stackup type to calculate Z0, effective Er, capacitance per inch, and inductance per inch in real time.
Design Insight: To achieve 50Ω on a standard FR4 stackup (Er ≈ 4.3), the trace width is typically close to the dielectric height (W/H ≈ 1.0–1.2 for microstrip). For 100Ω differential pairs, designers use narrower traces with controlled spacing. The fabricator's stackup table is your primary reference — always verify impedance targets with the fab's impedance calculator using their actual material data.
Wave Propagation
Signals Travel as Electromagnetic Waves
A digital signal on a PCB is not electrons moving from driver to receiver. It is an electromagnetic wave — coupled voltage and current waves that propagate together at the speed of light in the medium. The voltage wave exists in the electric field between trace and plane; the current wave flows in the signal conductor and returns through the reference plane directly beneath.
Energy is transported in the dielectric — not in the copper. The copper merely guides the electromagnetic field. This is why the dielectric constant (Er) determines propagation velocity, not the copper conductivity.
E-field (voltage) between trace & plane couples with H-field (current) to form a TEM wave that propagates along the line.
Power flows in the dielectric via the Poynting vector (E×H). Copper guides the wave but doesn't carry the energy.
At high frequencies, return current mirrors the signal trace path on the reference plane — forming the H-field loop.
Propagation Velocity Calculator
Propagation Delay
Signals Require Finite Time to Travel
Because signals travel at a finite velocity (roughly half the speed of light on FR4), every inch of PCB trace introduces a measurable delay. This propagation delay is critical for timing analysis in synchronous buses (DDR, LPDDR), clock distribution, and length-matching requirements.
Delay Calculator
Signal Launch Animation
Signal Propagation Visualizer
Watch a signal pulse launch from the driver, propagate along the transmission line, and arrive at the load. The voltage waveform, position marker, and time marker update in real time.
Reflection Theory
Reflections at Impedance Discontinuities
Whenever a traveling wave encounters a change in impedance — a different trace width, a connector, a via, or a mismatched termination — part of its energy reflects back toward the source. The severity of the reflection is determined by the reflection coefficient (Γ).
| Γ Value | Condition | Physical Meaning | Effect on Signal |
|---|---|---|---|
| 0 | ZL = Z0 | Perfect match | All energy absorbed. No reflection. |
| +1 | ZL = ∞ (open) | Open circuit | Full positive reflection. Voltage doubles. |
| −1 | ZL = 0 (short) | Short circuit | Full negative reflection. Voltage cancels. |
| 0 < |Γ| < 1 | ZL ≠ Z0 | Partial mismatch | Partial reflection — causes ringing. |
Reflection Impact on Received Signal
Compare the clean driver square wave with what the receiver sees after multiple reflections. Toggle between load impedances and observe ringing severity in real time.
Reflection Calculator
PCB Design Implications
Controlled Impedance in Practice
Modern high-speed interfaces mandate controlled impedance routing. The fabricator must maintain trace geometry within tight tolerances (±10% or better) across the entire board. Understanding how stackup parameters relate to impedance is essential for successful design sign-off.
40Ω SE data, 80Ω diff clocks. Tight length matching (±5 mil within byte lane). Fly-by topology.
85Ω diff pairs. Loss budget < 20dB at Nyquist. Back-drilling required for via stubs.
90Ω diff. Reference plane continuity critical. Connector launch optimization needed.
100Ω diff. Low-loss dielectric (Dk <3.5, Df <0.005). Channel compliance to IEEE specs.
100Ω diff. Maximum trace length constrained by loss. Careful via and connector transition design.
92–100Ω diff. Ultra-low-loss materials. Full-channel S-parameter simulation mandatory.
Module 2 Quiz
Select the best answer for each question.
- The clock frequency of the signal
- The DC resistance of the trace
- The ratio of propagation delay to signal rise time
- The number of PCB layers
- Z₀ = L × C per unit length
- Z₀ = √(L/C) where L and C are per unit length
- Z₀ = R × length (DC resistance)
- Z₀ = 1/√(LC) per unit length
- Γ = −0.5
- Γ = +0.33
- Γ = +0.5
- Γ = +1.0
- 25% of speed of light
- 50% of speed of light
- 70.7% of speed of light
- 100% of speed of light
- All energy is absorbed; no reflection occurs
- Half the energy is reflected
- The signal voltage doubles at the load
- The signal is completely attenuated
- Series inductance (L)
- Shunt capacitance (C)
- Series resistance (R) only
- Shunt conductance (G) — dielectric loss
- Impedance increases
- Impedance decreases
- No effect on impedance
- Depends on copper thickness only
- Γ = 0
- Γ = −1
- Γ = +0.5
- Γ = +1
- Stripline traces are always longer
- Copper on inner layers has higher resistance
- Fields are fully in dielectric — higher effective Er
- Two reference planes create more inductance
- 400 ps
- 667 ps
- 1.0 ns
- 1.5 ns
- 85 Ω differential
- 100 Ω differential
- 50 Ω single-ended
- 75 Ω single-ended
- Through the shortest geometric path on the ground plane
- Evenly distributed across all ground planes
- Directly beneath the signal trace on the reference plane
- Only through via connections between planes
- Increase Z₀ (less capacitance, more inductance)
- Decrease Z₀
- Not affect Z₀
- Only affect propagation delay, not Z₀
- Trace length > 1 inch
- Frequency > 100 MHz
- Propagation delay > rise time
- Propagation delay > rise time / 6
- Trace width
- Dielectric constant (Er)
- Dielectric height (H)
- Trace length
Engineering Challenge
Solve these real-world transmission line problems.
W=5mil, H=4mil, Er=4.3 (microstrip). Calculate Z0.
Calculate propagation delay for a 6-inch stripline trace (Er=4.3).
Z0=50Ω, ZL=75Ω. Calculate Γ and reflected voltage.
W/H = 5/4 = 1.25. Er_eff ≈ 3.2. Z0 ≈ 69Ω (microstrip Hammerstad equation). To get 50Ω, increase W to ~8 mil or decrease H.
Stripline: vp = c/√Er = 11.8/√4.3 = 5.69 in/ns. tpd = 6/5.69 = 1.054 ns.
Γ = (75−50)/(75+50) = 25/125 = +0.2. Vreflected = 0.2 × Vincident = 20% reflection.
Key Takeaways
What's Next: Module 3 — Impedance Matching covers termination strategies (series, parallel, AC, Thevenin), bounce diagrams, and practical termination design for real interfaces.